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Table 10.
CLK33 Routing Guidelines for PCI Device Down
Clock Group
Topology
Reference Plane
Characteristic Trace Impedance (Z
Trace Width
Trace Spacing
Trace Length – L1
Trace Length – L2
Resistor
Skew Requirements
† All trace width and spacing recommendations are derived from a target impedance and crosstalk sensitivity.
This is based on the stackup defined in
Figure 18.
Topology for CLK33 to PCI Slot
Clock
Driver
Table 11.
CLK33 Routing Guidelines for PCI Slot
Clock Group
Topology
Reference Plane
Characteristic Trace Impedance (Z
Trace Width
Trace Spacing
Trace Length – L1
Trace Length – L2
Trace Length – C
Resistor
Skew Requirements
Design Guide
®
Intel
Pentium
Parameter
CLK33
Point-to-Point
Ground referenced (contiguous over entire length)
50 Ω ± 10%
)
0
†
5 mils
†
25 mils
0.00 – 0.50"
3.00 – 9.00"
R1 = 33 Ω ± 5%
PCI device – PCI device skew max allowed by PCI Local Bus
Specification, Rev 2.2, is 2 ns. Therefore, length match with other
CLK33 signals within ± 1 ns.
L1
R1
Parameter
CLK33
Point-to-Point
Ground referenced (contiguous over entire length)
50 Ω ± 10%
)
0
5 mils
10 mils
0.00 – 0.50"
3.00 – 9.00"
Routed 2.50 inches per PCI Local Bus Specification, Rev 2.2
R1 = 33 Ω ± 5%
PCI device skew max allowed by PCI Local Bus Specification, Rev 2.2,
is 2 ns. Therefore, length match with other CLK33 signals within ± 1 ns.
®
M Processor and Intel
Platform Clock Routing Guidelines
Routing Guidelines
Section
3.1. Any deviation from this stackup must be simulated.
L2
PCI
Connector
Routing Guidelines
®
E7501 Chipset Platform
C
Trace On
PCI Card
PCI Device
51
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