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Intel BX80623G530 Specification

2nd generation intel core processor family desktop, intel pentium processor family desktop, and intel celeron processor family desktop, specification update
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2nd Generation Intel
Processor Family Desktop, Intel
Pentium
Desktop, and Intel
Processor Family Desktop
Specification Update
June 2013
Notice: Products may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
®
Processor Family
®
Core™
®
Celeron
Reference Number: 324643-029
®
®

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  • Page 1 ® 2nd Generation Intel Core™ ® Processor Family Desktop, Intel ® Pentium Processor Family ® ® Desktop, and Intel Celeron Processor Family Desktop Specification Update June 2013 Notice: Products may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
  • Page 2 MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND...

  • Page 3: Table Of Contents

     Contents Revision History ......................5 Preface ........................7 Summary Tables of Changes..................9 Identification Information ..................16 Errata ........................23 Specification Changes....................65 Specification Clarifications ..................66 Documentation Changes ..................67 § § Specification Update...
  • Page 4 Specification Update...

  • Page 5: Revision History

    Added Erratum BJ84, BJ85, BJ86, BJ87, BJ88 and BJ89 May 2011 Updated Processor Identification table to include the SKU information for ® -006 - 2nd Generation Intel Core™ i5-2310, i5-2405S and i3-2105 processors May 2011 ® - Intel® Pentium Processor G850, G840, G620 and G620T...

  • Page 6: April

    Revision Description Date -027 Added Erratum BJ122 April 2013 Added SKUs -028 May 2013 Added Errata BJ123-BJ125 -029 Added Errata BJ126-BJ128 June 2013 § § Specification Update...

  • Page 7: Preface

    Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual http:// ® Intel 64 and IA-32 Architectures Software Developer’s Manual download.intel.com/...
  • Page 8 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.

  • Page 9: Summary Tables Of Changes

    Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 10 Errata (Sheet 1 of 5) Steppings Number Status ERRATA An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ No Fix POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception No Fix APIC Error “Received Illegal Vector”...
  • Page 11 Wraps a 64-Kbyte Boundary in 16-Bit Code BJ40 No Fix Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation BJ41 No Fix Descriptors VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When vex.vvvv...
  • Page 12 C-state Exit Latencies May be Higher Than Expected MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control BJ61 No Fix Offset Field Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds BJ62 No Fix FFFFH BJ63 No Fix PCIe* Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s...
  • Page 13 No Fix A First Level Data Cache Parity Error May Result in Unexpected Behavior BJ96 No Fix Intel® Trusted Execution Technology ACM Revocation Programming PDIR And an Additional Precise PerfMon Event May Cause BJ97 Plan Fix Unexpected PMI or PEBS Events...
  • Page 14 The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated BJ123 No Fix After a UC Error is Logged ® BJ124 No Fix Spurious Intel VT-d Interrupts May Occur When the PFO Bit is Set BJ125 No Fix Processor May Livelock During On Demand Clock Modulation BJ126 No Fix...
  • Page 15  Documentation Changes Number DOCUMENTATION CHANGES On-Demand Clock Modulation Feature Clarification § § Specification Update...

  • Page 16: Identification Information

    The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, ® or Intel Core™ processor family. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family.
  • Page 17 Processor Production Top-side Markings (Example) ©'10 BRAND PROC# SLxxx SPEED [COO] [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 3) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared S-Spec Processor Processor DDR3 (MHz) / Stepping Technology L3 Cache...
  • Page 18 Table 1. Processor Identification (Sheet 2 of 3) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared S-Spec Processor Processor DDR3 (MHz) / Stepping Technology L3 Cache Notes Number Number Signature Processor 2.0 Frequency Size (MB) Graphics (GHz) Frequency 4 core: 2.8...
  • Page 19 Trusted Execution Technology (Intel TXT) enabled. ® ® ® ® Intel Virtualization Technology for IA-32, Intel 64 and Intel Architecture (Intel VT-x) enabled. ® ® Intel Virtualization Technology for Directed I/O (Intel VT-d) enabled. ® Intel AES-NI enabled. § § Specification Update...

  • Page 20: Errata

    Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of...
  • Page 21 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
  • Page 22 Developer's Manual Volume 3A: System Programming Guide, Part 1, in the section titled “Switching to Protected Mode” recommends the far JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
  • Page 23 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
  • Page 24 BJ12. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word Problem: Under a specific set of conditions, MMX stores (MOVD, MOVQ, MOVNTQ, MASKMOVQ) which cause memory access faults (#GP, #SS, #PF, or #AC), may incorrectly update the x87 FPU tag word register. This erratum will occur when the following additional conditions are also met: •The MMX store instruction must be the first MMX instruction to operate on x87 FPU state (i.e.
  • Page 25 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 26 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
  • Page 27 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 28 Under certain conditions as described in the Software Developers Manual section “Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this...
  • Page 29 Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel ® ® SpeedStep...

  • Page 30: Byte Count

    BJ32. Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid.
  • Page 31 Due to this erratum, the PCIe root port may not initiate a link speed change during some hardware scenarios causing the PCIe link to operate at a lower than expected speed. Intel has not observed this erratum with any commercially available platform. Workaround: None identified.
  • Page 32 If software clears the F (Fault) bit 127 of the Fault Recording Register (FRCD_REG at offset 0x208 in Remap Engine BAR) by writing 1b through RW1C command (Read Write ® 1 to Clear) when the F bit is already clear then a spurious interrupt from Intel VT-d ®...
  • Page 33 Upon detection of a non-zero bit in a reserved field, an Intel VT-d fault should be recorded. Due to this erratum, the processor does not check reserved bit values for Queued Invalidation descriptors.
  • Page 34 Accessing an unsupported field in VMCS will fail to properly report an error. In addition, VMREAD from an unsupported VMCS field may unexpectedly change its destination operand. Intel has not observed this erratum with any commercially available software. Workaround: Software should avoid accessing unsupported fields in a VMCS.
  • Page 35 The aliasing of memory regions, a condition necessary for this erratum to occur, ® is documented as being unsupported in the Intel 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
  • Page 36 BJ50. Perfmon Event LD_BLOCKS.STORE_FORWARD May Overcount Problem: Perfmon LD_BLOCKS.STORE_FORWARD (event 3H, umask 01H) may overcount in the cases of 4KB address aliasing and in some cases of blocked 32-byte AVX load operations. 4KB address aliasing happens when unrelated load and store that have different physical addresses appear to overlap due to partial address check done on the lower 12 bits of the address.
  • Page 37 Implication: Due to this erratum, an unexpected machine check with error code 0150H may occur, possibly resulting in a shutdown. Intel has not observed this erratum with any commercially available software. Workaround: Software should not write to a paging-structure entry in a way that would change, for any linear address, both the page size and the memory type.
  • Page 38 Implication: Due to this erratum, the processor may hang without reporting errors when receiving a malformed PCIe transaction. Intel has not observed this erratum with any commercially available device. Workaround: None identified.
  • Page 39 ® may be over twice the value specified in the Intel 64 and IA-32 Architectures Optimization Reference Manual and may lead to a delay in servicing interrupts. Intel has not observed any system failures due to this erratum. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 40 L1 power management mode is entered, further retrains initiated by software will not change speed to 2.5 GT/s. Implication: Intel has not observed any PCI Express device that changes supported link speed without actually initiating a speed change. Workaround: None identified.
  • Page 41 In this case, the store may cause a page fault or EPT violation that indicates that there is no translation for the page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was caused by a not-present page). Intel has not observed this erratum with any commercially available software.
  • Page 42 (TT1), while executing GETSEC[SENTER] or GETSEC[SEXIT] instructions, then under certain circumstances, the processor may hang. Implication: Possible hang during execution of GETSEC instruction. Intel has not been observed this erratum with any commercially available software. Workaround: None Identified.

  • Page 43: Branch Instructions

     BJ72. Unexpected #UD on VPEXTRD/VPINSRD Problem: Execution of the VPEXTRD or VPINSRD instructions outside of 64-bit mode with VEX.W set to 1 may erroneously cause a #UD (invalid-opcode exception). Implication: The affected instructions may produce unexpected invalid-opcode exceptions outside 64-bit mode.
  • Page 44 The graphics Command Streamer can get into a state that will effectively inhibit graphic RC6 (Render C6) power management state entry until render reset occurs. Any asynchronous Intel VT-d (Virtualization Technology for Directed I/O) access to IOTLB can potentially cause graphics Command Streamer to get into this RC6 inhibited state.
  • Page 45  BJ81. Execution of BIST During Cold RESET Will Result in a Machine Check Shutdown Problem: If BIST (Built In Self-Test) is enabled and a Cold RESET follows, an unrecoverable machine check shutdown will occur. Implication: Due to this erratum, BIST cannot be enabled. Workaround: None identified.
  • Page 46 BJ85. PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers Problem: In 64-bit mode, using REX.W=1 with PCMPESTRI and PCMPESTRM or VEX.W=1 with VPCMPESTRI and VPCMPESTRM should support a 64-bit length operation with RAX/ RDX. Due to this erratum, the length registers are incorrectly interpreted as 32-bit values.
  • Page 47 Implication: Software may see an unexpected page fault that indicates that there is no translation for the page. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 48 BJ91. Some Performance Monitoring Events in AnyThread Mode May Get Incorrect Count Problem: Performance monitoring AnyThread mode allows a given thread to monitor events as a result of any thread running on the same core. Due to this erratum, on systems with SMT enabled, counting any of the following performance monitoring events in AnyThread mode may get incorrect values: •INST_RETIRED;...
  • Page 49 Due to this erratum, 2nd_gen_i5_i7_SINIT_1.9.BIN and earlier will be revoked. ® Workaround: It is possible for the BIOS to contain a workaround for this erratum. All Intel enabled software must use SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN or later. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 50 BJ97. Programming PDIR And an Additional Precise PerfMon Event May Cause Unexpected PMI or PEBS Events Problem: PDIR (Precise Distribution for Instructions Retired) mechanism is activated by programming INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1. When PDIR is activated in PEBS (Precise Event Based Sampling) mode with an additional precise PerfMon event, an incorrect PMI or PEBS event may occur.
  • Page 51 Implication: Due to this erratum, the logical processor may hang. Intel's Software Developers Manual states “VMASKMOV should not be used to access memory mapped I/O and un- cached memory as the access and the ordering of the individual loads or stores it does is implementation specific.”...
  • Page 52 BJ103. Performance Monitor Precise Instruction Retired Event May Present Wrong Indications Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS mode), the processor may return wrong PEBS/PMI interrupts and/or incorrect counter values if the counter is reset with a SAV below 100 (Sample-After-Value is the counter reset value software programs in MSR IA32_PMC1[47:0] in order to control interrupt frequency).
  • Page 53  Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead of a #UD exception. Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of the VAESIMC and VAESKEYGENASSIST instructions. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 54 63:32. Because this erratum applies only to executions outside 64-bit mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to invalidate translations for a 64-bit guest. Intel has not observed this erratum with any commercially available software.
  • Page 55 Implication: Self- or cross-modifying code may not execute as expected. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Do not use floating-point stores to modify code.
  • Page 56 SEXIT doorbell event is serviced may be lost. Implication: Due to this erratum, there may be a loss of a debug exception when it happens concurrently with the execution of GETSEC[SEXIT]. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 57 1, further faults should not generate an interrupt. Due to this erratum, further interrupts may still occur. Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this erratum with any commercially available software. ®...
  • Page 58 "guest-physical address" field in the VMCS.) Implication: Software may not be easily able to determine the page offset of the original memory access that caused the EPT violation. Intel has not observed this erratum to impact the operation of any commercially available software. Workaround:...
  • Page 59  Implication: Software that uses the value reported in IA32_VMX_VMCS_ENUM[9:1] to read and write all VMCS fields may omit one field. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. § § Specification Update...

  • Page 60: Specification Changes

    Specification Changes The Specification Changes listed in this section apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®...

  • Page 61: Specification Clarifications

     Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®...

  • Page 62: Documentation Changes

    64 and IA-32 Architecture Software Developer's ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to become familiar with this file.
  • Page 63  Table 14-2. CPUID Signatures for Legacy Processors That Resolve to Higher Performance Setting of Conflicting Duty Cycle Requests DisplayFamily_Display DisplayFamily_Display DisplayFamily_Display DisplayFamily_Display Model Model Model Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 §...
  • Page 64 Specification Update...

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