Address And Control Topology For Two Discrete Sdram Devices; Address And Control Topology For Four Or More Discrete Sdram Devices - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
Figure 4-7.

Address and Control Topology for Two Discrete SDRAM Devices

80960RM /RN
I/O Processor
Figure 4-8.

Address and Control Topology for Four or More Discrete SDRAM Devices

8 0 9 6 0 R M / R N
I / O P r o c e s s o r
A p p l ic a b le t o a ll s i g n a l s e x c e p t
D Q [ 6 3 : 0 ] , S C B [ 7 : 0 ] , a n d S D Q M [ 7 : 0 ] .
18
Intel®
Applicable to all signals except
DQ[63:0], SCB[7:0], and SDQM[7:0].
I n t e l®
Signals m ust be 3 to 9.5
inches from the processor and
each SDRAM device
Address and Control
*
0 t o 0 . 5 i n c h
0 t o 0 . 5 i n c h
0 t o 0 . 5 i n c h
SDRAM 0
SDRAM 1
S D R A M 0
S D R A M 1
S D R A M 2
Design Guide