Cpu To Misp Bus Interface - Avaya Nortel Communication Server 1000 Reference

CPU to MISP bus interface

Information exchange between the CPU and the MISP is performed with packetized messages
transmitted over the CPU bus. This interface has a 16-bit data bus, an 18-bit address bus, and
interrupt and read/write control lines.
This interface uses shared Static Random Access Memory (SRAM) as a communication
exchange center between the CPU and the MPU. Both the CPU and the MPU can access this
memory over the transmit and receive channels on the bus.
MISP network bus interface
The network bus interface:
• converts bit interleaved serial data received from the network bus into byte interleaved
data for transmission over the 32 time slots used by the HDLC controller
• accepts byte interleaved data transmitted from the HDLC controller and converts it into a
bit interleaved data stream for transmission over the network bus
Power consumption
Power consumption is +5 V at 2 A; +15 V at 50 mA; and -15 V at 50 mA.
Circuit Card Reference
Functional description
July 2011 549