U Interface Logic - Avaya Nortel Communication Server 1000 Reference

The CardLAN interface is used for routine card maintenance, which includes polling the line
cards to find in which card slot the UILC is installed. It also queries the status and identification
of the card, and reports the configuration data and firmware version of the card.
The IPE bus interface connects one IPE bus loop that has 32 channels operating at 64 kbps
and one additional validation and signaling bit.
The Maintenance Signaling Channel (MSC) interface is used to communicate signaling and
card identification information from the Meridian 1 CPU to the UILC MCU. The signaling
information also contains maintenance instructions.
The digital pad provides gain or attenuation values to condition the level of the digitized
transmission signal according to the network loss plan. This sets transmission levels for the
B-channel circuit-switched voice calls.
The clock converter converts the 5.12 MHz clock from the IPE backplane into a 2.56 MHz clock
to time the IPE bus channels and an 8 kHz clock to provide PCM framing bits.
The PE interface logic consists of a Card-LAN interface, a PE bus interface, a maintenance
signaling channel interface, a digital pad, and a clock converter.
The Card-LAN interface is used for routine card maintenance, which includes polling the line
cards to find in which card slot the UILC is installed. It also queries the status and identification
of the card and reports the configuration data and firmware version of the card.
The PE bus interface connects one PE bus loop that has 32 channels operating at 64 kbps
and one additional validation and signaling bit.
The Maintenance Signaling Channel (MSC) interface communicates signaling and card
identification information from the CS 1000CPU to the UILC MCU. The signaling information
also contains maintenance instructions.
The digital pad provides gain or attenuation values to condition the level of the digitized
transmission signal according to the network loss plan. This sets transmission levels for B-
channel voice calls.
The clock converter converts the 5.12-MHz clock from the PE backplane into a 2.56-MHz clock
to time the PE bus channels and an 8-kHz clock to provide PCM framing bits.

U interface logic

The U interface logic consists of a transceiver circuit. It provides loop termination and high-
voltage protection to eliminate the external hazards on the DSL. The U interface supports voice
and data terminals, D-channel packet data terminals, and NT1s. A UILC has eight transceivers
to support eight DSLs for point-to-point operation.The U interface logic consists of a transceiver
circuit. It provides loop termination and high voltage protection to eliminate the external hazards
on the DSL. The U interface supports circuit-switched voice and data terminals, D-channel
packet data terminals, and NT1s. A UILC has eight transceivers to support eight DSLs for point-
to-point operation.
Circuit Card Reference
Functional description
July 2011 315