Card-Lan Interface - Avaya Nortel Communication Server 1000 Reference

Card-LAN interface

A Dual Port UART handles the functions of the serial ports for the Card-LAN serial link and the
echo canceller/test port interface. The echo/test interface is an asynchronous 4800 bps 8-bit
connected to port A of the UART. The Card-LAN interface is an asynchronous 19.2 kbps 9 bit
start/stop connected to port B of the UART.
The connection to the echo canceler/test port is available at the backplane/MDF connector.
The signals at this port conform to the EIA RS-232C standard.
Clock controller interface
The clock controller circuitry on the NTAK79 is identical to that of the NTAK20 clock
controller.
Though several DTI/PRI packs can exist in one system, only one clock controller may be
activated. All other DTI/PRI clock controllers must be switched off.
Clocking modes
The clock controller can operate in one of two modes:
• tracking
• non-tracking (also known as free-run)
Tracking mode
There are two stages to clock controller tracking:
• tracking a reference, and
• locked onto a reference.
When tracking a reference, the clock controller uses an algorithm to match its frequency to the
frequency of the incoming clock. When the frequencies are very near to being matched, the
clock controller is locked onto the reference. The clock controller makes small adjustments to
its own frequency until both the incoming and system frequencies correspond.
If the incoming clock reference is stable, the internal clock controller tracks it, locks onto it, and
matches frequencies exactly. Occasionally, however, environmental circumstances cause the
external or internal clocks to drift. When this happens, the internal clock controller briefly enters
the tracking stage. The green LED flashes momentarily until the clock controller is locked onto
the reference once again.
If the incoming reference is unstable, the internal clock controller remains continuously in the
tracking stage, with the LED flashing green all the time. This condition does not present a
problem, rather, it shows that the clock controller is continually attempting to lock onto the
Circuit Card Reference
Architecture
July 2011 531