Digital Phase Lock Loops - Avaya Nortel Communication Server 1000 Reference

Digital phase lock loops

The main digital PLL enables the clock controller to provide a system clock to the CPU. This
clock is both phase and frequency locked to a known incoming reference.
The hardware has a locking range of + 4.6 ppm for Stratum 3 and + 50 ppm for Stratum 4
(CCITT).
A second PLL on the clock controller provides the means for monitoring another reference.
Note that the error signal of this PLL is routed to the phase difference detector circuit so the
microprocessor can process it.
System clock specification and characteristics
As the accuracy requirements for CCITT and EIA Stratum 3 are different, it is necessary to
have two TCVCXOs which feature different values of frequency tuning sensitivity. See
225: System clock specification and characteristics
Table 225: System clock specification and characteristics
Specifications
Base Frequency
Accuracy
Operating Temperature
Drift Rate (Aging)
Tuning Range (minimum)
Input Voltage Range
EIA/CCITT compliance
The clock controller complies with 1.5 Mb EIA Stratum 3ND, 2.0 Mb CCITT or 2.56 Mb basic
rate. The differences between these requirements mainly affect PLL pull in range. Stratum 4
conforms to international markets (2.0 Mb) while Stratum 3 conforms to North American
markets (1.5 Mb).
Circuit Card Reference
CCITT
20.48 MHz
±3 ppm
0 to 70 C ±1 ppm
±1 ppm per year
±60 ppm min.
±90 ppm max.
0 to 10 volts, 5 V center
Functional description
on page 517.
EIA
20.48 MHz
±1 ppm
0 to 70 C ±1 ppm
±4 ppm in 20 years
±10 ppm min.
±15 ppm max.
0 to 10 volts, 5 V center
Table
July 2011 517