Ipe Interface Logic - Avaya Nortel Communication Server 1000 Reference

NT6D71 UILC line card
The serial control interface is an IPE bus that communicates with the U transceivers.
The MCU coordinates and controls the operation of the UILC. It has internal memory, a reset
and sanity timer, a serial control interface, a maintenance signaling channel, and a digital
pad.
The memory consists of 32 K of EPROM that contains the UILC operating program and 8 K of
RAM used to store interface selection and other functions connected with call activities.
The reset and sanity timer logic resets the MCU.
The serial control interface is an IPE bus used to communicate with the U transceivers.
The Micro Controller Unit (MCU) coordinates and controls the operation of the UILC. It has
internal memory, a reset and sanity timer, a serial control interface, a maintenance signaling
channel, and a digital pad.
The memory consists of 32 K of EPROM that contains the UILC operating program and 8 K of
RAM that stores interface selection and other functions connected with call activities.
The reset and sanity timer logic resets the MCU.
The serial control interface is a PE bus that communicates with U transceivers.

IPE interface logic

The IPE interface logic consists of a Card-LAN interface, a IPE bus interface, a maintenance
signaling channel interface, a digital pad, and a clock converter.
The Card-LAN interface is used for routine card maintenance, which includes polling the line
cards to find in which card slot the UILC is installed. It also queries the status and identification
of the card and reports the configuration data and firmware version of the card.
The IPE bus interface connects one IPE bus loop that has 32 channels operating at 64 kbps
and one additional validation and signaling bit.
The Maintenance Signaling Channel (MSC) interface communicates signaling and card
identification information from the system CPU to the UILC MCU. The signaling information
also contains maintenance instructions.
The digital pad provides gain or attenuation values to condition the level of the digitized
transmission signal according to the network loss plan. This sets transmission levels for B-
channel voice calls.
The clock converter converts the 5.12 MHz clock from the IPE backplane into a 2.56 MHz clock
to time the IPE bus channels and an 8-kHz clock to provide PCM framing bits.
The IPE interface logic consists of a Card-LAN interface, an IPE bus interface, a maintenance
signaling channel interface, a digital pad, and a clock converter.
314 Circuit Card Reference
Comments? infodev@avaya.com
July 2011