Avaya Nortel Communication Server 1000 Reference page 661

Clock rate converter
The 1.5 Mb clock is generated by a Phase-Locked Loop (PLL). The PLL synchronizes the 1.5
Mb DS1 clock to the 2.56 Mb system clock through the common multiple of 8 kHz by using the
main frame synchronization signal.
Circuit Card Reference
Architecture
July 2011 661