Table of Contents
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Figure
Number
1-1.
MPC823e Block Diagram .................................................................................1-7
1-2.
MPC823e System Configuration ....................................................................1-13
2-1.
MPC823e Signal Pinout ...................................................................................2-1
4-1.
Reset Configuration Basic Scheme .................................................................4-7
4-2.
Reset Configuration Sampling Scheme For Short PORESET Assertion .........4-8
4-3.
Reset Configuration Sampling Scheme For Long PORESET Assertion ..........4-8
4-4.
Reset Configuration Sampling Timing Requirements ......................................4-9
5-1.
Clock Source and Distribution ..........................................................................5-2
5-2.
Crystal Oscillator ............................................................................................5-10
5-3.
Clock Module Diagram ...................................................................................5-11
5-4.
SPLL Block Diagram ......................................................................................5-12
5-5.
Clock Dividers ................................................................................................5-15
5-6.
MPC823e Clocks Timing Diagram .................................................................5-16
5-7.
Selecting the General System Clock ..............................................................5-17
5-8.
Divided System Clocks Timing Diagram ........................................................5-18
5-9.
MPC823e Clocks For Division Factor 2 .........................................................5-18
5-10. CLKOUT Divider ............................................................................................5-19
5-11. BRGCLK Divider ............................................................................................5-19
5-12. SYNCCLK Divider ..........................................................................................5-20
5-13. LCDCLK Divider .............................................................................................5-21
5-14. LCD Clock Timing Diagram ............................................................................5-21
5-15. MPC823e Power Rails and TEXP Status ......................................................5-24
5-16. External Power Supply Scheme .....................................................................5-26
5-17. Register Lock Mechanism ..............................................................................5-28
MOTOROLA
LIST OF ILLUSTRATIONS
Title
Section 6
Introduction
Section 7
External Signals
Section 4
Reset
Section 5
Clocks and Power Control
MPC823e REFERENCE MANUAL
Page
Number
xxxi
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