Table of Contents
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TABLE OF CONTENTS (Continued)
Paragraph
Number
16.4.2.5
16.4.2.6
16.4.2.7
16.4.3
Initializing the Timers ..............................................................16-82
16.5
The SDMA Channels ........................................................................16-83
16.5.1
SDMA Bus Arbitration and Transfers .....................................16-85
16.5.2
The SDMA Registers ..............................................................16-86
16.5.2.1
16.5.2.2
16.5.2.3
16.5.2.4
16.6
Emulating IDMA ................................................................................16-90
16.6.1
Features .................................................................................16-91
16.6.2
IDMA Interface Signals ...........................................................16-91
16.6.2.1
16.6.3
IDMA Operation ......................................................................16-91
16.6.3.1
16.6.3.2
16.6.3.3
16.6.3.4
16.6.3.5
16.6.3.6
16.6.3.7
16.6.3.8
16.6.3.9
16.6.3.10
16.6.3.11
16.6.3.11.1
16.6.3.11.2
16.6.3.11.3
16.6.3.11.4
16.6.3.12
16.6.3.13
16.6.3.14
16.6.3.15
16.6.3.16
16.7
The Serial Interface with Time-Slot Assigner ..................................16-113
16.7.1
Features ...............................................................................16-115
16.7.2
Configuring the Time-Slot Assigner ......................................16-115
16.7.3
Enabling Connections to the Time-Slot Assigner .................16-118
16.7.4
Serial Interface RAM Operation ...........................................16-118
16.7.4.1
MOTOROLA
Title
Timer Capture Registers .............................................16-81
Timer Counter Registers .............................................16-81
Timer Event Registers ................................................16-82
SDMA Configuration Register .....................................16-86
SDMA Status Register ................................................16-88
SDMA Mask Register .................................................16-89
SDMA Address Register .............................................16-90
DREQx and SDACKx .................................................16-91
AutoBuffer and Buffer Chaining ..................................16-92
IDMA Parameter RAM Memory Map ..........................16-93
IDMA Status Registers ...............................................16-95
IDMA Mask Registers .................................................16-96
IDMA Buffer Descriptors .............................................16-97
IDMA Commands .....................................................16-101
Starting IDMA ...........................................................16-102
Requesting IDMA Transfers .....................................16-102
Level-Sensitive Mode ...............................................16-102
Edge-Sensitive Mode ................................................16-102
IDMA Operand Transfers ..........................................16-103
Transfer Identification ...................................16-103
Dual-Address Mode .....................................16-103
Single-Address Mode (Fly-By Transfers) .....16-104
Single-Buffer Burst Fly-By Mode ..................16-106
IDMA Status Registers .............................................16-110
IDMA Mask Registers ...............................................16-111
Single-Buffer Timing .................................................16-111
DownLoad Sequence ...............................................16-112
Bus Exceptions .........................................................16-113
One Multiplexed Channel with Static Frames ...........16-119
MPC823e REFERENCE MANUAL
Page
Number
xv
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