On-Chip Cache Memories; Instruction Cache - Motorola MC68030 User Manual

SECTION 6

ON-CHIP CACHE MEMORIES

The MC68030 microprocessor includes a 256-byte on-chip instruction cache and a 256-byte
on-chip data cache that are accessed by logical (virtual) addresses. These caches improve
performance by reducing external bus activity and increasing instruction throughput.
Reduced external bus activity increases overall performance by increasing the availability
of the bus for use by external devices (in systems with more than one bus master, such as
a processor and a DMA device) without degrading the performance of the MC68030. An
increase in instruction throughput results when instruction words and data required by a
program are available in the on-chip caches and the time required to access them on the
external bus is eliminated. Additionally, instruction throughput increases when instruction
words and data can be accessed simultaneously.
As shown in Figure 6-1, the instruction cache and the data cache are connected to separate
on-chip address and data buses. The address buses are combined to provide the logical
address to the memory management unit (MMU). The MC68030 initiates an access to the
appropriate cache for the requested instruction or data operand at the same time that it
initiates an access for the translation of the logical address in the address translation cache
of the MMU. When a hit occurs in the instruction or data cache and the MMU validates the
access on a write, the information is transferred from the cache (on a read) or to the cache
and the bus controller (on a write). When a hit does not occur, the MMU translation of the
address is used for an external bus cycle to obtain the instruction or operand. Regardless
of whether or not the required operand is located in one of the on-chip caches, the address
translation cache of the MMU performs logical-to-physical address translation in parallel
with the cache lookup in case an external cycle is required.
MOTOROLA MC68030 USER'S MANUAL 6-1