Routing Guidelines For Common Clock Signals; Wired-Or Signals; Agtl+ Common Clock I/O Signals - Intel Xeon Design Manual

System Bus Routing Guidelines
Therefore, the PCB trace length of DSTB0 must be within ±25 mils of 4.356" from Processor 0 to
Processor 1.
Calculate CPU to MCH length assuming the CPU to MCH PCB length to be 9.0":
CPU
pin
MCH
MCH
CPU1
CPU1
CPU
pin
+ CPU1
= 0.280 + 9.000 + 0.273 – 0.190 – 0.117
CPU
pin
Therefore, the PCB trace length of DSTB0 must be within ± 25 mils of 9.246" from Processor 1
to the MCH.
5.2

Routing Guidelines for Common Clock Signals

Table 5-5
Table 5-5. AGTL+ Common Clock I/O Signals
Signal Types
Input
I/O
Route the common clock signals according to the processor system bus topology shown in
Figure 5-1. Routing guidelines for the common clock signal group are in
traces with at least 50% of the trace width directly over a reference plane.
5.2.1

Wired-OR Signals

There are five "wired-OR" signals on the system bus. These signals are HIT#, HITM#, MCERR#,
BINIT#, and BNR#. These signals differ from the other system bus signals in that more than one
agent can be driving the signal at the same time. However, Intel recommends that special attention
be given to the routing of these signals in adherence to the layout guidelines presented in
Timing and signal integrity must be met for the cases where one agent is driving, all agents are
driving, and any combination of agents are driving.
The wired-OR signals should follow the same routing rules as the common clock signals. Intel
recommends that simulations for these signals be performed for each system.
58
-to-MCH (HD4) (motherboard trace from Processor 0 to Processor1) = 9.000"
pin
(DSTBP0) (strobe package trace length) = 0.190"
pkg_len
(HD4) (HD4 package trace length) = 0.280"
pkg_len
(DSTBP0) = 0.78 * CPU
pkg_comp
(HD4) = 0.78 * CPU1
pkg_comp
-to-MCH (DSTBP0) = MCH
pin
(HD4) – MCH
pkg_comp
-to-MCH (DSTBP0) = 9.246"
pin
lists the Common clock signals.
BPRI#, BR[3:1]#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,
HITM#, LOCK#, MCERR#
(DSTBP0) = 0.78 * 0.150" = 0.117"
pkg_len
(HD4) = 0.78 * 0.350" = 0.273"
pkg_len
(HD4) + CPU
pkg_len pin
(DSTBP0) – CPU1
pkg_len
Signals
-to-MCH (HD4)
pin
(DSTBP0)
pkg_comp
Table 5-2. Route the
Table
Design Guide
5-2.