Phase Lock Loop (Pll) And Filter; Voltage Identification (Vid); Phase Lock Loop (Pll) Filter Requirements - Intel Xeon Datasheet

2.3.2

Phase Lock Loop (PLL) and Filter

V and V
CCA
processor with 800 MHz system bus. Since these PLLs are analog in nature, they require quiet
power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O
timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation,
these supplies must be low pass filtered from V
The AC low-pass requirements are as follows:
•
< 0.2 dB gain in pass band
•
< 0.5 dB attenuation in pass band < 1 Hz
•
> 34 dB attenuation from 1 MHz to 66 MHz
•
> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in
Figure 1.

Phase Lock Loop (PLL) Filter Requirements

NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
3. f , if existent, should be less than 0.05 MHz.
peak
4. f represents the maximum core frequency supported by the platform.
core
2.4

Voltage Identification (VID)

The Voltage Identification (VID) specification for the Intel® Xeon™ processor with 800 MHz
system bus is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-
Down (EVRD) 10.0 Design Guidelines and Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 10.1 Design Guidelines. The voltage set by the VID signals is the
maximum voltage allowed by the processor (please see
specifications). VID signals are open drain outputs, which must be pulled up to V
Datasheet
are power sources required by the PLL clock generators on the Intel® Xeon™
CCIOPLL
0.2 dB
0 dB
x dB
–28 dB
–34 dB
DC 1 Hz
Passband
Intel® Xeon™ Processor with 800 MHz System Bus
.
TT
Figure 1.
fpeak 1 MHz 66 MHz
<50 kHz
High
Frequency
(core frequency).
core
Section 2.11.2
fcore 1.67 GHz
500 MHz
CS00141
for V overshoot
CC
. Please refer to
TT
15