Intel ® Ich3-S Quadrant Layout; Intel ® Ich3-S Quadrant Layout (Top View) - Intel Xeon Design Manual

Processor with 512 kb l2 cache and intel e7500 chipset platform
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Component Quadrant Layout
®
2.3
Intel
®
Figure 2-3. Intel
ICH3-S Quadrant Layout (Top View)
PCI
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
LPC
O
V
O
W
O
Y
AA
AB
AC
O
1
2
GPIO
LPC/Firm Ware
LAN
AC'97
EEPROM
NC
GPIO
RTC
28
ICH3-S Quadrant Layout
LAN
3
4
5
6
7
8
9
10
O
O
O
O
O
O
O
3
4
5
6
7
8
9
10
SMBus
VSS
VCC_1.8
VCCSUS_1.8
VCC_3.3
VCCSUS_3.3
O
Misc. VCC
11
12
13
14
15
16
17
18
11
12
13
14
15
16
17
18
IDE
CLK
IDE
HUB Interface
USB
CPU
SMBus
USB
19
20
21
22
23
A
B
C
O
D
O
O
O
E
O
O
F
O
O
O
O
G
O
O
H
J
K
L
M
HUB
N
Interface
P
R
T
U
V
W
CPU
Y
AA
AB
AC
19
20
21
22
23
Design Guide

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