Asynchronous Gtl+ Signals Driven By The Processor; Topology For Asynchronous Gtl+ Signals Driven By The Processor - Intel Xeon Design Manual

System Bus Routing Guidelines
Table 5-6. Asynchronous GTL+ and Miscellaneous Signals (Sheet 2 of 2)
Signal Name
SM_DAT
SM_EP_A[2:0]
SM_TS_A[1:0]
SM_WP
SMI#
STPCLK#
THERMTRIP#
VCCA
VCCIOPLL
VCCSENSE
VID[4:0]
GTLREF
VSSA
VSSSENSE
5.3.1

Asynchronous GTL+ Signals Driven by the Processor

Follow the topology shown in
THERMTRIP#. Note that FERR# is the only signal in this group that connects the processors to the
ICH3-S. IERR#, PROCHOT# and THERMTRIP# connect to other motherboard logic (such as the
Baseboard Management Controller) and may need voltage translation logic, depending on the
motherboard receiver logic devices used. Do not route a stub when routing to the processors.
Figure 5-4. Topology for Asynchronous GTL+ Signals Driven by the Processor
Ω
56
NOTES:
1. Trace Z
2. Trace spacing = 10 mil.
60
Type
SMBUS (3.3 V)
SMBUS (3.3 V)
SMBUS (3.3 V)
SMBUS (3.3 V)
Async GTL+
Async GTL+
Async GTL+
Power
Power
Other
Other
Power
Power
Other
Figure 5-4
VCC_CPU
Processor 0
± 5%
0.1" – 3.0" 0.1" – 10.0"
= 50 Ω.
0
Processor
Driven By
I/O Type
I/O Processor/Controller
I Pull-up / Pull-down
I Pull-up / Pull-down
I External Logic
I ICH3-S
I ICH3-S
O Processor
I Pull-up / Pull-down
I Pull-up / Pull-down
O Processor
O Processor
I Pull-up / Pull-down
I Pull-up / Pull-down
O Processor
when routing FERR#, IERR#, PROCHOT# and
Processor 1
or other logic
0.1" – 10.0"
Received By
Processor/Controller
Processor
Processor
Processor
Processor
Processor
External Logic
Processor
Processor
Voltage Regulator
Voltage Regulator
Processor
Processor
Voltage Regulator
VCC_CPU
®
Intel
Ω
56
ICH3-S
0.1" – 10.0"
Design Guide
± 5%