Dual Channel Source Clocked Signal Group Routing; Dual Channel Source Clocked Signal Group Routing Guidelines - Intel Xeon Design Manual

Processor and e7500/e7501 chipset compatible platform. addendum for embedded applications
Hide thumbs Also See for Xeon:
Table of Contents

Advertisement

®
Intel
Xeon™ Processor and Intel
Figure 11. Dual Channel 2-DIMM Command Clock Topology
NOTES:
1. CMDCLK/CMDCLK# must be matched to within ± 2 mils using package trace length compensation.
2. Unused CMDCLK/CMDCLK# pairs are no connects.
3. Indicated lengths measure from the MCH component pin to the DIMM connector pin.
3.2.3

Dual Channel Source Clocked Signal Group Routing

The MCH drives the command clock signals and the source-clocked signals together. That is, the
MCH drives the command clock in the center of the valid window, and the source-clocked signals
propagate with the command clock signal. Therefore, the critical timing is the difference between
the command clock flight time and the source clocked signal flight time. The absolute flight time is
not as critical.
When resistor packs are used for the termination resistors, it is suggested that data group signals
not be mixed with Source Clocked, Chip Select, or Clock Enable signals within the same resistor
pack for validation purposes.
Table 10. Dual Channel Source Clocked Signal Group Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
MCH to DIMM1 Trace
Length
DIMM to DIMM Trace
Length
DIMM to Rtt Trace Length
Termination Resistor (Rtt)
MCH Breakout Guidelines
NOTES:
1. No length tuning required.
2. See the Intel
26
®
E7500/E7501 Chipset Compatible Platform
A_CMDCLK0 & CMDCLK0#
Channel A
A_CMDCLK1 & CMDCLK1#
MCH
B_CMDCLK0 & CMDCLK0#
Channel B
B_CMDCLK1 & CMDCLK1#
1-DIMM Solution
0°, 25°, 90°
1,2
50 Ω ± 10%
5 mils
15 mils
1.8" to 5.5"
Not Applicable
< 0.8"
39.2 Ω ± 1%
5/5, < 500 mils
®
Xeon™ Processor and Intel
DIMMs
2-DIMM Solution
25°
RAS#, CAS#, WE#, MA[12:0], BA[1:0]
Daisy Chain
Ground
50 Ω ± 10%
5 mils
15 mils
1.8" to 5.5"
1.8" to 2.2"
< 0.8"
39.2 Ω ± 1%
5/5, < 500 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide.
Platform Design Guide Addendum
2-DIMM Solution
Reference
90°
50 Ω ± 10%
5 mils
15 mils
Note 2
1.8" to 5.5"
1.0" to 1.2"
< 0.8"
39.2 Ω ± 1%
5/5, < 500 mils

Advertisement

Table of Contents
loading

This manual is also suitable for:

E7500E7501

Table of Contents