System Overview
5.6
VRD VID Headers
Provides for manual control of the processor core voltage regulator output level(s). Normally, the
processor should be run at its default VID (voltage identification) value as set during
manufacturing. However, in the event the user needs to set a different VID value from the default
value, it can be accomplished through a jumper block found on the board. Note that these headers
are not populated by default.
The CPU 0 VID header is located at J9K2. CPU 1 VID header is located at J4K1.
the VID settings available via the VID headers.
Table 5.
Processor VRD Settings (Sheet 1 of 2)
VID5
VID4
VID3
VID2
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
®
30
Intel
Xeon™ Processor, Intel
V
CC_MAX
VID1
VID0
(V)
0
1
0
0.8375
0
0
1
0.8500
0
0
1
0.8625
0
0
0
0.8750
0
0
0
0.8875
1
1
1
0.9000
1
1
1
0.9125
1
1
0
0.9250
1
1
0
0.9375
1
0
1
0.9500
1
0
1
0.9625
1
0
0
0.9750
1
0
0
0.9875
0
1
1
1.0000
0
1
1
1.0125
0
1
0
1.0250
0
1
0
1.0375
0
0
1
1.0500
0
0
1
1.0625
0
0
0
1.0750
0
0
0
1.0875
1
1
1
OFF
®
E7520 Chipset, Intel
VID5
VID4
VID3
VID2
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
1
®
6300ESB ICH Development Kit User's Manual
Table 5
provides
V
CC_MAX
VID1
VID0
(V)
1
0
1.2125
0
1
1.2250
0
1
1.2375
0
0
1.2500
0
0
1.2625
1
1
1.2750
1
1
1.2875
1
0
1.3000
1
0
1.3125
0
1
1.3250
0
1
1.3375
0
0
1.3500
0
0
1.3625
1
1
1.3750
1
1
1.3875
1
0
1.400
1
0
1.4125
0
1
1.4250
0
1
1.4375
0
0
1.4500
0
0
1.4625
1
1
1.4750