Hot Plug Muxed Signals In Single Slot Parallel Mode; Mux Circuit Example; Single Slot Parallel Mode Hot Plug Signal Table - Intel Xeon Design Manual

Figure 8-10. MUX Circuit Example
This signal could be
pulled up to VCC_3.3
depending on the
strapping need.
8.2.5.6

Hot Plug Muxed Signals in Single Slot Parallel Mode

The Hot Plug signals that connect to the controller are as follows:
Table 8-10. Single Slot Parallel Mode Hot Plug Signal Table
Signal
HxSWITCHA
HxFAULTA#
HxPRSNT2A#
HxPRSNT1A#
HxM66ENA
HxPCIXCAP1A
HxPCIXCAP2A
HxRESETA#
HxGNLEDA
HxAMLEDA
HxBUSENA#
HxCLKENA#
HxPWRENA
1. HPx_SLOT [N] are pull-ups/pull-downs. When in dual slot parallel mode, the external logic that decodes the
three-state value of PCIXCAP from the card must actively drive these signals to either logic 1 or logic 0 to
overcome the value of the pull-up/pull-down, and must be tri-stated during reset and while the card is not
connected to avoid damaging the slot count value.
2. The P64H2 must drive this signal to its corresponding state shown in
for single slot parallel mode so that LEDs are in the appropriate state (off), and the Q-switches remain
disconnected. Note that the placement of the signals should be such that the value driven by the P64H2 in
dual slot parallel mode is the same value it would have driven if in serial mode.
3. In parallel mode, the BUSEN# and CLKEN# signals become active low instead of active high as they are
during serial mode.
Design Guide
1 k Ω
2:1 Multiplexer
S 1
PCIXCAP1 / PCIXCAP2 S 2
PWROK
Type
Bus A
I PA_IRQ[15]
I PA_IRQ[14]
I PA_IRQ[13]
I PA_IRQ[12]
I/O PA_IRQ[11]
I HPA_SLOT[2]
I HPA_SLOT[1]
O PA_GNT[5]
O HPA_SOC
O HPA_SOL
O HPA_SORR#
HPA_SIL#
O
HPA_SOD
O
D
(PCIXCAP1 / PCIXCAP2) or HPxSLOT Strap
VCC_3.3
8.2 kΩ
C ENB
Muxed With
Ball #
F4 PB_IRQ[15]
E4 PB_IRQ[14]
F5 PB_IRQ[13]
E5 PB_IRQ[12]
D5 PB_IRQ[11]
D20 HPB_SLOT[2]
C20 HPB_SLOT[1]
E22 PB_GNT[5]
A19 HPB_SOC
D19 HPB_SOL
A18 HPB_SORR#
D24 HPB_SIL#
B19 HPB_SOD
®
Intel 82870P2 (P64H2)
Truth Table
C (PWROK) D
0 HPxSLOT Strap
1 PCIXCAP1 / PCIXCAP2
Bus B Ball #
F1
E1
D1
C1
B1
D23
C23
G4
A24
C22
A22
D24
C24
Table 8-11 in case the system is set up
Note
1
1
2
2
2
2, 3
2, 3
2
105