Testhi[6:0] Routing Guidelines; Sktocc# Signal Routing Guidelines - Intel Xeon Design Manual

Processor with 512 kb l2 cache and intel e7500 chipset platform
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5.3.8

TESTHI[6:0] Routing Guidelines

All TESTHI[6:0] pins must be connected to VCC_CPU via pull-up resistors with a termination
value within 20% of the signal impedance (50 Ω ± 20%). TESTHI[3:0] may all be tied together and
pulled up to VCC_CPU with a single, 50 Ω ± 20% resistor if desired. TESTHI[6:5] may also be
tied together and pulled up to VCC_CPU with a single 50 Ω ± 20% resistor. However, boundary
scan testing will not be functional if any TESTHI pins are pulled up together. TESTHI4 must
always be pulled up independently from the other TESTHI pins regardless of the usage of
boundary scan.
5.3.9

SKTOCC# Signal Routing Guidelines

The SKTOCC# signal is an output from the processor used as an indication of whether a processor
is installed or not. It is asserted low when a processor is installed in the socket, and floats when no
processor is present. If this signal is used on the board, the designer can use a pull-up to prevent
floating. SKTOCC# can be used to disable the VRM or VRD output for unpopulated processor
sockets or the power supply output when no processors are installed and other features.
Design Guide
System Bus Routing Guidelines
65

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