Platform Clocking; Clock Block Diagram - Intel 6300ESB ICH User Manual
Processor with 800 mhz system bus, chipset and development kit
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Also See for 6300ESB ICH:
- Design manual (14 pages) ,
- Datasheet (848 pages) ,
- Design manual (320 pages)
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System Overview
5.2
Platform Clocking
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the
100 MHz differential clock to the DB800. The DB800 then generates the 100 MHz differential pair
clock for the PCI Express* devices.
Figure 6.
Clock Block Diagram
CPU0_ CLK
CPU1_ CLK
ITP_ CLK
MCH_ CLK
MCH_66MHZ_CLK
ICH_US _48MHZ_CLK
LPZ_14MHZ_CLK
ICH_33MHZ_CLK
ICH_H166MHZ_CLK
ICH_PX66MHZ_CLK
SIO_33MHZ_CLK
LPC_14MHZ_CLK
LAI_H166MHZ_CLK
D 800_SRC_100MHZ_CLK
VIDEO_33MHZ_CLK
FWH_33MHZ_CLK
PORT80_33MHZ_CLK
PCI_SLOT6_33MHZ_CLK
CK-409
®
26
Intel
Xeon™ Processor, Intel
Figure 6
shows the CRB clock configuration.
CPU0
CPU1
DDRA_CMDCLK[1:0]
ITP
DDR _CMDCLK[1:0]
MCH
Intel ®
ICH_PX_PCLK0[1:0]
6300ESB
I/O
Controller
Hub
32.786 MHz
SIO
HI LAI
29.499 MHz
Video
FWH
Port 80
PCI 2.2
®
®
E7520 Chipset, Intel
DDRA
DDRB
PCI-X
PXH_SRC_
100MHZ_CLK
EXP_SLOT5_
100MHZ_CLK
EXP_SLOT6_
100MHZ_CLK
DB800
6300ESB ICH Development Kit User's Manual
PCI-X
PXH
PCI Express Slot
PCI Express Slot
2937-03
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