Revision History - Intel Xeon Design Manual

Processor with 512 kb l2 cache and intel e7500 chipset platform
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Revision History

Revision
14
-001
Initial Release.
Changed: Section 6.3; DDR Command Clock Figure Notes
Added: Section 12.5.4; New P64H2 Power Sequencing
-002
Requirement
Updated Schematics to reflect changes identified above.
Description
Date
February 2002
March 2002
Design Guide

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