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Platform Power Delivery Guidelines
®
Table 12-9. Intel
ICH3-S Decoupling Recommendations
Power
V_CPU_IO
VCCRTC
VCC_3.3
VCCSUS_3.3
VCC_1.8
VCCSUS_1.8
5VREF_SUS
V5_REF
184
Decoupling Requirements
Use one 0.1 µF decoupling capacitor.
Use one 1.0 µF decoupling capacitor.
See
Figure 9-10
for the External Circuitry.
Requires six 0.1 µF decoupling capacitors.
Requires two 0.1 µF decoupling capacitors.
Requires four 0.1 µF decoupling capacitors.
Requires one 0.1 µF decoupling capacitor.
Requires one 0.1 µF decoupling capacitor.
V5REF_SUS is the reference voltage for some 5 V
tolerant inputs in the ICH3-S (USB data and over
current signals). V5REF_SUS must power up before
or simultaneous to VCCSUS_3.3. It must power
down after or simultaneous to VCCSUS_3.3. (For
most platforms, this power sequencing is not an
issue as VCCSUS_3.3 is derived from
5VREF_SUS.)
Requires one 0.1 µF decoupling capacitor.
V5_REF is the reference voltage for most 5 V
tolerant inputs in the ICH3-S. Tie to pins V5REF[2:1].
V5REF must power up before or simultaneous to
VCC_3.3. It must power down after or simultaneous
to VCC_3.3.
Decoupling Placement
• Locate within 100 mils of the
ICH3-S processor interface balls.
• Locate within 100 mils of the
VCCRTC interface ball (ball
AB6).
• Distribute around the ICH3-S
package sides within 100 mils of
the package balls:
– Top near AUX/PCI
– Left across the PCI and LPC
– Bottom near IDE
– Right near GPIO[43]
• Place one capacitor on the top
side within 200 mils of the USB
center.
• Place one capacitor on the
bottom side near the
VCCSUS_3.3 supply.
• Locate 2 capacitors distributed
local to the hub interface, within
50 mils of the package HI balls.
• Distribute the remaining
capacitors on the left and bottom
sides of the package for core
delivery.
• Locate within 200 mils of the
ICH3-S, Balls B23 and C23.
Design Guide
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