Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Specification
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Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Specification

Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Specification

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®
Intel
Xeon

Specification Update

January 2007
®
®
Notice: The Intel
Xeon
processor may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are
documented in this specification update.
®
Processor
Document Number: 249678-057

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Summary of Contents for Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

  • Page 1: Specification Update

    Processor Specification Update January 2007 ® ® Notice: The Intel Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
  • Page 2 INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.

  • Page 3: Table Of Contents

    Revision History ......................... 5 Preface ..........................9 Identification Information ....................10 Mixed Steppings in DP Systems ..................18 Summary Table of Changes..................... 20 Errata..........................27 Specification Changes...................... 51 Specification Clarifications ....................53 Documentation Changes....................56 ® ® Intel Xeon Processor Specification Update...
  • Page 4 ® ® Intel Xeon Processor Specification Update...

  • Page 5: Revision History

    • Added errata P48. • Updated errata P11. • Added Specification Changes P1-P3. • Added Documentation Changes P1-P3. • Added new S-specs SL687 and SL65T to Processor ID table. • Updated datasheet name to 2.40 GHz. ® ® Intel Xeon Processor Specification Update...
  • Page 6 ® ® • Added Low Voltage Intel Xeon Processor Specifications. -027 • Added erratum P60. June 2003 ® ® • Updated Sections with Low Voltage Intel Xeon Processor Datasheets. • Updated erratum P53. ® ® Intel Xeon Processor Specification Update...
  • Page 7 • Added New S-specs to the processor ID table for 0F25H (M0 Stepping) and 0F29h (D1 Stepping). • Added new processor with Processor Signature=0F29H (D1 Stepping). ® ® • Updated DP Platform Population Matrix for the Intel Xeon Processor to include 0F25H and 0F29H. • Removed Specification Clarification P3.
  • Page 8 • Updated the Software Developer Manual Name. -055 November 2006 • Made changes to the DP Platform Population Matrix. -056 December 2006 • Updated Summary Table of Changes. -057 • Updated Summary Table of Changes. January 2007 ® ® Intel Xeon Processor Specification Update...

  • Page 9: Preface

    Care should be taken to read all notes associated with each S-Spec number. ® ® Errata are design defects or errors. Errata may cause the Intel Xeon processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 10: Identification Information

    Identification Information Identification Information ® ® Intel Xeon Processor Markings, 256-KB Cache (603-pin Interposer INT-mPGA Package) Figure 1. Top Side Processor Marking 2D Matrix Intel® Xeon™ Dynamic Laser i(m) ©’01 Mark Area ATPO Mark (8 Characters) D0096109 0032 Serial Number Mark (4 digits) Figure 2.
  • Page 11 Processor, 512-KB Cache, 400 and 533 MHz FSB Markings, (603-pin Interposer INT-mPGA Package and 604-pin Fc-mPGA2 Package) Figure 3. Top Side Processor Marking Intel® Xeon™ i m c ‘02 2D Matrix Includes ATPO and Serial Number (front end mark) Figure 4. Bottom Side Processor Marking...
  • Page 12 S-Spec and Assembly Site FPO and Serial Number 1700DP/256L2/400/1.7V (End of Line Mark) SL56N COSTA RICA C0096109-0021 Pin A1 Triangle The Intel Xeon processor can be identified by the following values: Family Model Brand ID 1111 0000 00001110 1111...
  • Page 13 Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the Processor Signature instruction is executed with a 2 in the EAX register. Please refer to the Intel Processor Identification and the Processor Signature Instruction Application Note (AP-485) for further information on the Processor Signature instruction.
  • Page 14 Identification Information ® ® Table 1. Intel Xeon Processor Identification and Package Information (Sheet 2 of 5) Speed Processor S-Spec Core Processor Core/Front L2 Size L3 Size Package and Interposer Notes Number Stepping Signature Side Bus (Kbytes) (Kbytes) Revision Revision...
  • Page 15 Identification Information ® ® Table 1. Intel Xeon Processor Identification and Package Information (Sheet 3 of 5) Speed Processor S-Spec Core Processor Core/Front L2 Size L3 Size Package and Interposer Notes Number Stepping Signature Side Bus (Kbytes) (Kbytes) Revision Revision...
  • Page 16 Identification Information ® ® Table 1. Intel Xeon Processor Identification and Package Information (Sheet 4 of 5) Speed Processor S-Spec Core Processor Core/Front L2 Size L3 Size Package and Interposer Notes Number Stepping Signature Side Bus (Kbytes) (Kbytes) Revision Revision...
  • Page 17 5. These parts are the Intel Xeon Processor with 533 MHz Front Side Bus. 6. These parts have a VID of 1.525V. ® ® 7. These parts are the Low Voltage Intel Xeon Processor. ® ® 8. These parts are the Intel Xeon Processor with 1-MB L3 Cache.

  • Page 18: Mixed Steppings In Dp Systems

    • Intel requires that the proper microcode update be loaded on each processor operating in a multiprocessor system. Any processor that does not have the proper microcode update loaded is considered by Intel to be operating out of specification.
  • Page 19 ® ® ® ® 2. This Matrix also applies to the Intel Xeon Processor with 533 MHz Front Side Bus, Low Voltage Intel Xeon Processor, ® ® ® ® Intel...

  • Page 20: Summary Table Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 21 AH= Intel Core™2 Duo mobile Processor ® ® Intel Core™2 Extreme Processor X6800 and Intel Core™2 Duo Desktop Processor E6000 Sequence AJ = Quad-Core Intel® Xeon® Processor 5300 Series ® ® Dual-Core Intel Xeon Processor 7100 Series Dual-Core Intel Xeon Processor 3000 Series ®...
  • Page 22 Fixed Bus invalidate line requests that returns unexpected data may result in L1 cache corruption Fixed Multiprocessor boot protocol may not complete with an IOQ depth of one ® ® Intel Xeon Processor Specification Update...
  • Page 23 (BWL) transaction to occur to the same cache line address as an outstanding bus read line (BRL) or bus read-invalidate line (BRIL) Fixed L2 cache may contain stale data in the exclusive state ® ® Intel Xeon Processor Specification Update...
  • Page 24 #GP exception handler No Fix Locks and SMC detection may cause the processor to temporarily hang No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on a FP instruction ® ® Intel Xeon Processor Specification Update...
  • Page 25 REP MOVS/STOS instruction with Fast Strings enabled No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt No Fix The Processor May Report a #TS Instead of a #GP Fault ® ® Intel Xeon Processor Specification Update...
  • Page 26 Context ID feature added to processor signature instruction feature Flags/IA32_MISC_Enable registers Specification Clarifications SPECIFICATION CLARIFICATIONS Maximum ITCC specification correction Specification Clarification with respect to Time-Stamp Counter Documentation Changes DOCUMENTATION CHANGES None for this revision of the Specification Update. ® ® Intel Xeon Processor Specification Update...

  • Page 27: Errata

    Problem: invalid opcode 0FFFh did not require a ModRM in previous generation microprocessors such as Pentium II or Pentium III processors, but it is required in the Intel Xeon processor Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on the Intel Xeon processor.
  • Page 28 When fast strings are enabled and a REP MOV instruction is used to move a string and the source Problem: and destination strings overlap by 56 bytes or less, data corruption may occur. ® ® Intel Xeon Processor Specification Update...
  • Page 29 When an L1 cache parity error occurs, the cache controller logic should write the physical address of the data memory location that produced that error into the IA32_MC1_ADDR REGISTER (MC1_ADDR). In some instances of a parity error on a load operation that hits ® ® Intel Xeon Processor Specification Update...
  • Page 30 If a valid address is not available, the Address Valid bit in the IA32_MC1_Status register should not be set. In instances where an L1 parity error ® ® Intel Xeon Processor Specification Update...
  • Page 31 UC load will reduce the occurrence of this erratum. Certain debug mechanisms do not function as expected on the processor. Implication: None at this time. Workaround: Status: For the steppings affected, see the Summary Table of Changes. ® ® Intel Xeon Processor Specification Update...
  • Page 32 EMON event counting of x87 loads may not work as expected If a performance counter is set to count x87 loads and floating-point (FP) exceptions are unmasked, Problem: the FPU Operand (Data) Pointer (FDP) may become corrupted. ® ® Intel Xeon Processor Specification Update...
  • Page 33 Another processor issues a snoop to the same address as the LRFO. An internal boundary condition exists which may prevent the LRFO from completing correctly causing the snoop to receive incorrect data. Intel has not been able to reproduce this erratum with commercial software.
  • Page 34 Errata corrected page tables are left in a non-accessed or non-modified state) the processor may livelock. Intel has not been able to reproduce this erratum with commercial software. Implication: This erratum occurs in systems where page tables are being modified by other processors. If this erratum is encountered, the processor will livelock resulting in a system hang or operating system failure.
  • Page 35 Remove the software’s dependency on the fact that #AC has precedence over #PF. Alternately, correct the page-fault in the page-fault handler and then restart the faulting instruction. For the steppings affected, see the Summary Table of Changes. Status: ® ® Intel Xeon Processor Specification Update...
  • Page 36 UC address translation with the DTLB, an unintended UnCacheable load operation may be sent out on the system bus. When this erratum occurs, an unintended load may be sent on system bus. Intel has only Implication: encountered this erratum during pre-silicon simulation.
  • Page 37 0 count. Ensure that at least one CCCR/counter in the same group as the tagging ESCR is enabled for those Workaround: performance metrics that require 2 ESCRs and tagging uops for at-retirement counting. ® ® Intel Xeon Processor Specification Update...
  • Page 38 The incorrect data is corrected before the completion of the LSS instruction but the value of CR2 and the error code pushed on the stack are reflective of the speculative state. Intel has not observed this erratum with commercially available software.
  • Page 39 0 to 1, this erratum may result in software failures. It is possible for BIOS code to contain a workaround for this erratum. Workaround: For the steppings affected, see the Summary Table of Changes. Status: ® ® Intel Xeon Processor Specification Update...
  • Page 40 If a cache line (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid (I) state in the L1 cache and it's adjacent sector (B) is in the Invalid (I) state and the following scenario occurs: ® ® Intel Xeon Processor Specification Update...
  • Page 41 The write-back from the WC Buffers completes leaving stale data, for cache line A, in the Exclusive (E) state in the L2 cache. Stale data may be consumed leading to unpredictable program execution. Intel has not been able to Implication: reproduce this erratum in commercial software.
  • Page 42 This will force the store to the APIC register before any subsequent instructions are executed. No commercial operating system is known to be impacted by this erratum. Status: For the steppings affected, see the Summary Table of Changes. ® ® Intel Xeon Processor Specification Update...
  • Page 43 If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the Problem: processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software. None at this time. Workaround: For the steppings affected, see the Summary Table of Changes.
  • Page 44 RF flag (in the EFLAGS register image) to be incorrect. The RF flag is normally used for code breakpoint management during debug of an application. It is Implication: not typically used during normal program execution. Code breakpoints or single step debug ® ® Intel Xeon Processor Specification Update...
  • Page 45 Workaround: None at this time. For the steppings effected, see the Summary Table of Changes. Status: ® ® Intel Xeon Processor Specification Update...
  • Page 46 FP event, the load in the microcode routine will trigger the data breakpoint resulting in a debug exception (#DB). An incorrect #DB may occur if data breakpoint is placed on an FP instruction. Intel has not Implication: observed this erratum with any commercially available software or system.
  • Page 47 The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as ® being unsupported in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3, Section 10.12.4 However, if this erratum occurs the system may hang.
  • Page 48 ® younger memory access. Refer to the IA-32 Intel Architecture Software Developer’s Manual for ® the correct way to update page tables. Software that conforms to the IA-32 Intel Architecture Software Developer’s Manual will operate correctly. ® Implication: If the guidelines in the IA-32 Intel Architecture Software Developer’s Manual are not followed,...
  • Page 49 Define BTS/PREBS buffer such that BTS/PREBS absolute maximum minus BTS/PREBS buffer ® base is integer multiple of the corresponding record sizes as recommended in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3. For the steppings affected, see the Summary Table of Changes.
  • Page 50 CR2. Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed this erratum with any commercially available software.

  • Page 51: Specification Changes

    64 and IA-32 Intel Architectures Software Developer’s Manual, Volumes 1, 2A, 2B, 3A, and 3B (Order Numbers 253665, 253666, 253667, and 253668, respectively) ® All Specification Changes will be incorporated into a future version of the appropriate Intel ® Xeon processor documentation.
  • Page 52 Context ID. A value of ‘1’ indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of ‘0’ this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for more details. ® ® Intel Xeon Processor Specification Update...

  • Page 53: Specification Clarifications

    Architectures Software Developer’s Manual, Volumes 1, 2A, 2B, 3A, and 3B (Order Numbers 253665, 253666, 253667, and 253668, respectively) All Specification Clarifications will be incorporated into a future version of the appropriate Intel Xeon processor documentation. Maximum ITCC specification correction The maximum I specification has been corrected.
  • Page 54 10 years after being reset. The period for counter wrap is longer for Pentium 4, Intel Xeon, P6 family, and Pentium processors. Normally, the RDTSC instruction can be executed by programs and procedures running at any privilege level and in virtual-8086 mode.
  • Page 55 The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).

  • Page 56: Documentation Changes

    64 and IA-32 Intel Architectures Software Developer’s Manual, volumes 1, 2A, 2B, 3A, and 3B will be posted in the separate document IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.

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