Table of Contents
Advertisement
I/O Controller Hub
9.7.2.6
Board Design
The following recommendations are based on a ground referenced design.
•
Top Layer Routing
Sensitive analog signals are routed completely on the top layer without the use of vias. This
allows tight control of signal integrity, and removes any impedance inconsistencies due to
layer changes.
•
Ground Plane
A layout split (100 mils) of the ground plane under the magnetics module between the primary
and secondary side of the module is recommended. It is also recommended to minimize the
digital noise injected into the 82562 common ground plane. Suggestions include optimizing
decoupling on neighboring noisy digital components, isolating the 82562 digital ground using
a ground cutout, etc.
•
Power Plane
Physically separate digital and analog power planes must be provided to prevent digital
switching noise from being coupled into the analog power supply plane's VDD_A. Analog
power may be a metal fill "island," separated and RC filtered from digital power.
•
Signal Layer Routing
The digital high-speed signals, which include all of the LAN interconnect interface signals,
must be routed on an internal signal layer away from the analog signals.
9.7.2.7
Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN On
Motherboard Designs:
•
Unequal length of the two traces within a differential pair. Inequalities create common-mode
noise and will distort the transmit or receive waveforms.
•
Lack of symmetry between the two traces within a differential pair. (For each component and/
or via that one trace encounters, the other trace must encounter the same component or a via at
the same distance from the PLC.) Asymmetry can create common-mode noise and distort the
waveforms.
•
Excessive distance between the PLC and the magnetics or between the magnetics and the
RJ-45/11 connector. Beyond a total distance of about 4 inches, it can become extremely
difficult to design a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy
substrate) will attenuate the analog signals. In addition, any impedance mismatch in the traces
will be aggravated if they are long. The magnetics should be as close to the connector as
possible (≤ one inch).
•
Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the
transmit channel can cause excessive emissions (failing FCC), and can cause poor transmit
BER on long cables. At a minimum, other signals should be kept 0.3 inch from the differential
traces.
•
Routing the transmit differential traces next to the receive differential traces. The transmit
trace that is closest to one of the receive traces will put more crosstalk onto the closest receive
trace and can greatly degrade the receiver's BER over long cables. After exiting the PLC, the
transmit traces should be kept 0.3 inch or more away from the nearest receive trace. The only
possible exceptions are in the vicinities where the traces enter or exit the magnetics, the
RJ-45/11, and the PLC.
140
Design Guide
Advertisement
Table of Contents
