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13.2
MCH Schematic Checklist
L
Table 13-2. MCH Schematic Checklist (Sheet 1 of 3)
Checklist Items
Host Interface
ADS#
AP[1:0]
BINIT#
BNR#
BPRI#
1
BREQ0#
CPURST#
DBI[3:0]#
DBSY#
DEFER#
DP[3:0]#
DRDY#
HA[35:3]#
HD[63:0]#
HADSTB[1:0]#
HDSTBN[3:0]#
HDSTBP[3:0]#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
9
HTRDY#
RS[2:0]#
RSP#
10
XERR#
DDR Interfaces A & B / Connector
DQ[63:0]
CB[7:0]
DQS[17:0]
MA[12:0]
BA[1:0]
RAS#
CAS#
WE#
CS[7:0]#
CMDCLK[3:0]
CMDCLK[3:0]#
CKE
RCVENIN#
RCVENOUT#
DDRCOMP
DDRCVOL
DDRCVOH
Design Guide
Recommendations
• See processor section of this checklist.
2
3
4
5
6
7
8
• Place a 10 Ω ± 2% series resistor between
MCH and first DIMM. Resistor Packs can be
used. Terminate these signals to DDR VTERM
(1.25 V) through a 22 Ω ± 2% resistor.
• Terminate these signals to DDR VTERM
(1.25 V) through a 22 Ω ± 2% resistor.
• Terminate these signals to DDR VTERM
(1.25 V) through a 22 Ω ± 2% resistor.
• Connect directly to the corresponding DIMM.
• Terminate CKE to DDR VTERM (1.25 V)
through a 22 Ω ± 2% resistor.
• Route RCVENOUT# to RCVENIN#. Place a
47 Ω ± 2% parallel resistor to DDR VTERM as
close as possible to the MCH on the
RCVENIN# side. Refer to
• Pull-up to DDR VTERM (1.25 V) through a
6.81 Ω ± 1% resistor.
• Connect as shown in
Figure
6-13.
Figure
6-15.
Schematic Checklist
Comments
• Signal Integrity.
• Refer to
Section
6.2.
• Refer to
Section
6.4.
• Signal Integrity.
• Refer to
Section
6.5.
• Signal Integrity.
• Refer to
Section
6.3.
• Refer to
Section
6.6.
• Refer to
Section
6.7.
• Refer to
Section
6.8.
• Refer to
Section
6.8.
193
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