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9.6.7
SUSCLK
SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the
quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be
between 30% and 70%.
If the SUSCLK duty cycle is beyond the 30%–70% range, there is a poor oscillation signal on
RTCX1 and RTCX2.
SUSCLK can be probed directly using a normal probe (50 Ω input impedance probe), and it is an
appropriate signal to check the RTC frequency to determine the accuracy of the ICH3-S RTC
clock.
9.6.8
RTC-Well Input Strap Requirements
All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC
or pulled down to ground while in the G3 state. RTCRST#, when configured as shown in
Figure
9-13, meets this requirement. RSMRST# should have a weak external pull-down to ground,
and INTRUDER# should have a weak external pull-up to VCCRTC. This will prevent these nodes
from floating in G3, and correspondingly will prevent ICCRTC leakage that can cause excessive
coin-cell drain. The PWROK input signal should also be configured with an external weak
pull-down.
9.7
Internal LAN Layout Guidelines
The ICH3-S provides various options for integrated LAN capability. The platform supports several
components depending on the target market. The guidelines use the term 82562ET to refer to both
the 82562ET, and the 82562EM. The 82562EM is specified in those cases where a difference
exists.
Platform LAN Connect
Component
82562EM
82562ET
Design guidelines are provided for each required interface and connection. Refer to
and
Table 9-1
Design Guide
Connection
Advanced 10/100 Ethernet
10/100 Ethernet
for the corresponding section of the design guide.
I/O Controller Hub
Features
Alert on LAN* & Ethernet 10/100 Connection
Ethernet 10/100 Connection
Figure 9-14
133
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