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14.2
Intel
Table 14-2. MCH Layout Checklist (Sheet 1 of 3)
Checklist Items
Host Interface
ADS#
AP[1:0]
BINIT#
BNR#
BPRI#
1
BREQ0#
CPURST#
DBSY#
DEFER#
HA[35:3]#
HD[63:0]#
HADSTB[1:0]#
HDSTBN[3:0]#
HDSTBP[3:0]#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
9
HTRDY#
DP[3:0]#
DRDY#
RS[2:0]#
RSP#
10
XERR#
DBI[3:0]#
DDR Interfaces A & B / Connector
General
Guidelines
Design Guide
E7500 MCH Layout Checklist
Recommendations
• See processor section of this checklist.
2
3
4
5
6
7
8
• Route interface 50 Ω nominal impedance,
± 10%.
• 5 on 15 is maintained for Data/Strobe/
CMD signals; 5 on 7 is maintained for CK/
CK# signals.
• If using the recommended stackup, outer
layer routing of DDR signals should be
kept to a minimum (except for reference
voltages). Via up close to passive
devices, and immediately via back down
following the device.
• Try to maintain same ground reference
when transitioning layers—add stitching
via if reference plane changes.
• Connect termination resistors directly to
termination plane (flood is on outer layer).
• Space traces out as much as possible
through the DIMMs.
• All traces are routed 1.8" to 6.0" from
MCH to first DIMM connector, and 0.8" to
1.2" between connectors.
Layout Checklist
Comments
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