Asynchronous Gtl+ Signals Driven By The Chipset; Voltage Translation For Init; Topology For Asynchronous Gtl+ Signals Driven By The Chipset - Intel Xeon Design Manual

Intel
2.3.2

Asynchronous GTL+ Signals Driven by the Chipset

Follow the topology shown in
CPUSLP#, SMI#, STPCLK#, LINIT[1:0] and PWRGOOD.
Figure 4. Topology for Asynchronous GTL+ Signals Driven by the Chipset
VCC_CPU
Note:
2.3.2.1

Voltage Translation for INIT#

A voltage translator circuit is required for the INIT# signal for all platforms that use FWH. The
required routing topology for INIT# is given in
processors.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
Figure 4
200Ω ± 5%
Processor
0
3 inches max
Trace Zo - 50Ω
Trace Spacing = 10 ml
Figure 6 shows the voltage translator circuit.
®
E7500/E7501 Chipset Compatible Platform
when routing A20M#, IGNNE#, INIT#, NMI, INTR,
1 to 12 inches
Figure 5. Do not route a stub when routing to the
ICH3-S
A9047-02
17