V/V5Ref Sequencing; Example 1.8 V/3.3 V Power Sequencing Circuit - Intel Xeon Design Manual

Platform Power Delivery Guidelines
Figure 12-21. Example 1.8 V/3.3 V Power Sequencing Circuit
When analyzing systems that may be "marginally compliant" to the 2 V Rule, attention must be
paid to the behavior of the ICH3-S's RSMRST# and PWROK signals because they control internal
isolation logic between the various power planes:
•
RSMRST# controls isolation between the RTC well and the resume wells.
•
PWROK controls isolation between the resume wells and main wells.
If one of these signals goes high while one of its associated power planes is active and the other is
not, a leakage path will exist between the active and inactive power wells. This could result in high,
possibly damaging, internal currents.
12.4.2

3.3V/V5REF Sequencing

V5REF is the reference voltage for 5 V tolerance on inputs to the ICH3-S. V5REF must be
powered up before VCC3_3, or after VCC3_3 within 0.7 V. Also, V5REF must power down after
VCC3_3, or before VCC3_3 within 0.7 V. The rule must be followed in order to ensure the safety
of the ICH3-S. If the rule is violated, internal diodes will attempt to draw power sufficient to
damage the diodes from the VCC3_3 rail.
satisfy the V5REF/3.3V sequencing rule.
This rule also applies to the standby rails, but in most platforms, the VCCSUS3_3 rail is derived
from the VCCSUS5 rail and therefore, the VCCSUS3_3 rail will always come up after the
VCCSUS5 rail. As a result, V5REF_SUS will always be powered up before VCCSUS3_3. In
platforms that do not derive the VCCSUS3_3 rail from the VCCSUS5 rail, this rule must be
enforced on the platform.
182
+3.3V
220 Ω
220 Ω
Q2
NPN
470 Ω
+1.8V
Q1
PNP
Table 12-22 shows a sample implementation of how to
Design Guide