Input Voltages And Currents; Power Good Output (Pwrgd); Power Distribution Block Diagrams For Two-Way System Motherboard - Intel Xeon Design Manual

Figure 12-2. Power Distribution Block Diagrams for Two-Way System Motherboard
Power
Supply
Power
Supply
The voltage regulator should be capable of accepting a 5-bit VID code, which is used to indicate
the maximum voltage allowed by the individual processor unit. The VID values are documented in
®
the Intel
12.2.4.1

Input Voltages and Currents

To minimize power distribution losses, the recommended main power source for the VR is 12 V
+5%, 8%. This voltage is supplied by a conventional server power supply such as the SSI
–
EPS-12V. The system designer should ensure that the input circuit of the VR incorporates the
necessary local bulk bypassing on the 12 V rail.
12.2.4.2

Power Good Output (PWRGD)

The VR should provide an open collector or equivalent Power Good signal consistent with TTL
DC levels. This signal should transition to the open (>100 kΩ) state within 10 ms of the output
voltage stabilizing within the specified processor operating voltage range. The signal should be in
the low impedance (to ground) state whenever VCC_CPU is outside of the required range, and
should be in the open state whenever VCC_CPU is within its specified range. At power up, the
PWRGD signal must remain in the low-impedance state until the output voltage has stabilized
within the required tolerance.
The minimum voltage at which PWRGD is asserted should be the minimum VCC_CPU specified
in the Intel
Datasheet, minus margin to prevent false de-assertion, but at least 95% of (VID minus 125 mV).
The maximum voltage at which PWRGD is asserted should be the VID set-point voltage, plus
margin to prevent false de-assertion, but must be no greater than (VID plus 250 mV).
This PWRGD should be capable of sinking up to 4 mA while maintaining a voltage of 0.4 V or
lower. When the output is in the open state, it should be capable of withstanding up to 5.5 V. Latch-
up or damage cannot occur if the pull-up voltage on the system board is present with no +12 V
input present. VR Power Good should remain low if the VR is disabled by the Output Enable
(OUTEN) pin.
Design Guide
Voltage Regulator Module 1
Voltage Regulator Module 2
Voltage Regulator
Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet.
®
Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz
Platform Power Delivery Guidelines
Down
Processor 0
Processor 1
Processor 0
Processor 1
165