Proper Power Good Usage; Voltage Translation For Init; Topology For Pwrgood (Cpupwrgood); Init# Routing Topology - Intel Xeon Design Manual

System Bus Routing Guidelines
5.3.2.1

Proper Power Good Usage

Route CPUPWRGD as shown in
voltage regulator and processor pair in order to recognize individual voltage regulator failures.
Figure 5-7. Topology for PWRGOOD (CPUPWRGOOD)
300
NOTES:
1. Trace Z
2. Trace spacing = 10 mil.
5.3.2.2

Voltage Translation for INIT#

A voltage translator circuit is required for the INIT# signal for all platforms that use the FWH. The
required routing topology for INIT# is given in
processors.
Figure 5-8. INIT# Routing Topology
Ω
200
NOTE: The total trace length between the ICH3-S pin and the Processor 0 pin must be less than 15 inches.
62
Figure
VCC_CPU
Processor 0
Ω
± 5%
0.1" – 3.0"
= 50 Ω.
0
Figure 5-9 shows the voltage translator circuit.
VCC_CPU
Processor 0
± 5%
0.1" – 3.0"
5-7. You may choose to isolate PWRGOOD for each
Processor 1
0.1" – 9.0" 0.1" – 9.0"
Figure 5-8. Do not route a stub when routing to the
Processor 1
0.1" – 9.0" 0.1" – 9.0"
®
Intel
ICH3-S
FW H
®
Intel
ICH3-S
Voltage
Translator
0.1" – 9.0"
Design Guide