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Debug Port
The debug port design information can be found in a separate document. The routing of the signals,
the signal levels, and all other information required to develop a debug port on this platform can be
found in the ITP700 Debug Port Design Guide.
10.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging the system bus of Intel Xeon processors. Contact Tektronix, Inc. and Agilent
Technologies to get specific information about their logic analyzer interfaces. The following
information is general in nature. Specific information must be obtained from the logic analyzer
vendor.
Due to the complexity of these systems, the LAI is critical in providing the ability to probe and
capture system bus signals. There are two sets of considerations to keep in mind when designing a
system that can make use of an LAI: mechanical and electrical.
10.2
Mechanical Considerations
The LAI is installed between the processor socket and the microprocessor. The LAI pins plug into
the socket, and the microprocessor pins plug into a socket on the LAI. Cabling that is part of the
LAI egresses the system to allow an electrical connection between the microprocessor and a logic
analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the
cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system.
10.3
Electrical Considerations
The LAI also affects the electrical performance of the system bus. Therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that the tool will work in the system. Contact the logic analyzer vendor for electrical
specifications and load models for the LAI solution it provides
Design Guide
Debug Port
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