Clock Driver Decoupling; Decoupling Capacitors Placement And Connectivity - Intel Xeon Design Manual

Platform Clock Routing Guidelines
4.2

Clock Driver Decoupling

The decoupling requirements for a CK408B compliant clock synthesizer are as follows:
•
One, 22 µF polarized (decoupling) capacitor placed close to the VDD generation circuitry.
•
Eleven, 0.1 µF high-frequency decoupling capacitors placed close to the VDD pins on the
clock driver.
•
Three, 0.1 µF high-frequency decoupling capacitors placed close to the VDDA pins on the
clock driver.
•
One, 10 µF polarized (decoupling) capacitor placed close to the VDDA pins on the clock
driver.
•
One, 0.1 µF high-frequency decoupling capacitor placed close to the VDDA generation
circuitry.
•
All decoupling capacitors should be placed close to the clock driver pins. Refer to
Figure 4-15. Decoupling Capacitors Placement and Connectivity
VSS pins goes through vias on the ground flood to ground plane
Ground vias
Ground vias
Ground vias
Ground vias
Ground vias
50
VSS
Pin 1
VDD
Pin 2
XTAL_IN
Pin 3
XTAL-OUT
VDD
VSS Pin 4
Pin 5
PCIF0
PCIF1 Pin 6
Pin 7
PCIF2
VSS
Pin 8
VDD
VSS Pin 9
PCI0
VDD
Pin 10
PCI1
Pin 11
PCI2
Pin 12
PCI3
Pin 13
VSS
Pin 14
VDD
VSS Pin 15
VDD
Ground Flood
PCI4 Pin 16
PCI5
Pin 17
PCI6 Pin 18
VSS
Pin 19
VDD
Pin 20
VSS
VDD 66BUFF0/
Pin 21
3V66_2
66BUFF/-
Pin 22
3V66_3
66BUFF2/
Pin 23
3V66_4
Pin 24
66IN/3V66_5
VDDA PWRDWN_N Pin 25
VDDA
Pin 26
FB4
VSSA
Pin 27
VTT_PWRGD_
Pin 28
N
VSS
Place the caps as close
as possible to the pins
Power vias
CK408B
REF0
Pin 56
Pin 55 S1
CPU3
Pin 54
CPU/3
Pin 53
CPU0
Pin 52
CPU/0
Pin 51
VDD
Pin 50
CPU1
Pin 49
Pin 48
CPU/1
Pin 47 VSS
VDD
Pin 46
CPU2
Pin 45
CPU/2
VDD
Pin 44
VSS MULT0
Pin 43
Pin 42 IREF
Pin 41
VSS-IREF
S2
Pin 40
Pin 39 USB 48MHz
Pin 38
DOT 48MHz
Pin 37
VDD-48MHz
Pin 36
VSS-48MHz
Pin 35
3V66_1/VCH
PCI_STOP_N
Pin 34
3V66_0
Pin 33
Pin 32 VDD
Pin 31 VSS
VDD
Pin 30 SCLK
Pin 29 SDATA
Figure
VSS
Ground vias
VDD
VSS
Ground vias
VDDA
FB4
Ground vias
VSS
VSS
Ground vias
Design Guide
4-15.