Hub Interface 2.0 Implementation; Hub Interface 2.0 High-Speed Routing Guidelines; Hub Interface 2.0 Signal/Strobe Association; Hub Interface 2.0 Signal Groups - Intel Xeon Design Manual

Hub Interface
7.2

Hub Interface 2.0 Implementation

The MCH, and P64H2 ballout assignments are optimized to simplify the hub interface routing
between these devices. To allow for greater flexibility in design, a connector can be placed on the
interface to access a HI2.0 agent that resides on an adapter card. The typical card implementation
uses an extension to the 3.3 V PCI-64 connector that provides an additional 70 pins for HI2.0.
Power, JTAG and SMBus signals are taken from the PCI portion of the connector. The remaining
PCI signals are unused. This approach provides the flexibility to allow either a
PCI/PCI-X card or a HI2.0 card, to be populated in the slot.
For the 16-bit Hub Interface, HI[7:0] and HI[20] are associated with PSTRBF and PSTRBS, and
HI[15:8] and HI[21] are associated with PUSTRBF and PUSTRBS. HI[19:16] are common clock
signals; they are sampled using CLK66. The three hub interfaces on the MCH are functionally and
electrically identical. Therefore, these guidelines apply to all three hub interfaces.
Table 7-1. Hub Interface 2.0 Signal/Strobe Association
7.2.1

Hub Interface 2.0 High-Speed Routing Guidelines

This section documents the routing guidelines for the Hub Interface 2.0. The Hub Interface 2.0
signal groups are listed in
signals are given in
Table 7-2. Hub Interface 2.0 Signal Groups
Common Clock Signals
Source Synchronous Signals
Miscellaneous Signals
NOTE: x = B, C, or D
Table 7-3. Hub Interface 2.0 Routing Parameters
System Type
533 MHz
84
Data Group
HI[7:0]
HI[20]
HI[15:8]
HI[21]
Table 7-2. The general routing guidelines for the Hub Interface 2.0
Table 7-3.
Group
HI[19:16]_x
HI[21:20]_x, HI[15:0]_x,
PSTRBF, PSTRBS, PUSTRBF,
PUSTRBS
HIRCOMP_x, HISWNG_x,
HIVREF_x
Trace Length Trace Length
Min-Max
(For HI2.0 (For HI2.0 Card
Device Down)
3" – 20"
Associated Strobes
PSTRBF
PSTRBS
PUSTRBF
PUSTRBS
MCH
Min-Max
Trace Zo
Solution)
50 Ω ± 10%
3" – 14"
Signal
®
Intel P64H2
HI[19:16]
HI[21:20],HI[15:0],
PSTRBF, PSTRBS, PUSTRBF,
PUSTRBS
HI_RCOMP, HI_VSWING,
HI_VREF
Trace Breakout
Width/Spacing Width/Spacing
5/15 mils 5/5 mils
(max dist = 0.5")
Design Guide