Platform System Clock-Reference - Intel Xeon Design Manual

Processor with 512 kb l2 cache and intel e7500 chipset platform
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Platform Clock Routing Guidelines
Table 4-2. Platform System Clock-Reference
Clock Group
Host_CLK
CLK66
CLK33_ICH3-S
CLK14
CLK33
USBCLK
36
CK-408B Pin
Component
CPU#
Debug Port
CPU
Debug Port
CPU#
Processor 0
CPU
Processor 0
CPU#
Processor 1
CPU
Processor 1
CPU#
MCH
CPU
MCH
66BUF
MCH
ICH3-S
P64H2
PCIF
ICH3-S
REF0
ICH3-S
SIO
PCI
PCI Connector #1
PCI Connector #2
PCI Connector #3
PCI Connector #4
PCI Connector #5
FWH
SIO
PCIF
BMC
USB-48MHZ
ICH3-S
Component Pin Name
BCLK[0]
BCLK[1]
BCLK[0]
BCLK[1]
BCLK[0]
BCLK[1]
HCLKINP
HCLKINN
66IN
CLK66
CLK66
PCICLK
CLK14
CLOCKl
CLK
CLK
CLK
CLK
CLK
CLK
PCI_CLK
LCLK
CLK48
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