Single Channel Clock Enable Routing; Single Channel Cke Topology - Intel Xeon Design Manual

Processor and e7500/e7501 chipset compatible platform. addendum for embedded applications
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Intel
3.3.6

Single Channel Clock Enable Routing

The MCH provides a single clock enable (CKE) signal. This signal is used during initialization to
indicate that valid power and clocks are being applied to the DIMMs. Because the CKE signal has
higher loading, it requires a lower impedance. The recommended impedance for the CKE signal is
40 Ω. This may be achieved using a 7.5-mils wide trace on the recommended stack-up (refer to
Figure
16). It is acceptable to route the CKE signal 5 mils wide with 5 mils spacing when breaking
out of the MCH. However, the trace must be widened to 7.5 mils before widening the spacing to 15
mils. The CKE signal requires a parallel termination resistor (Rtt) to DDR VTERM placed as close
to the last DIMM connector as possible.
Table 19. Single Channel Clock Enable Routing Guidelines
Parameter
1,2
Signal Group
Topology
Reference Plane
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
MCH to DIMM1 Trace Length
DIMM to DIMM Trace Length
CKE Stub Trace Length
DIMM to Rtt Trace Length
Termination Resistor (Rtt)
MCH Breakout Guidelines
NOTES:
1. No length tuning required.
®
2. See the Intel
Xeon™ Processor and Intel
.
Figure 21. Single Channel CKE Topology
MCH
NOTE: Indicated lengths measure from the MCH component pin to the DIMM connector pin.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
1-DIMM Solution
0°, 25°, 90°
40 Ω ± 10%
7.5 mils
15 mils
1.8" to 6.0"
Not Applicable
< 300 mils
< 0.8"
39.2 Ω ± 1%
5/5, < 500 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide .
CKE Stub
CKE
Channel A
MCH to DIMM1
®
E7500/E7501 Chipset Compatible Platform
2-DIMM Solution
2-DIMM Solution
25°
CKE
Daisy Chain with Stubs
Ground
40 Ω ± 10%
40 Ω ± 10%
7.5 mils
15 mils
1.8" to 6.0"
1.8" to 6.0"
1.0" to 2.2"
0.50" to 1.2"
< 300 mils
< 300 mils
< 0.8"
39.2 Ω ± 1%
39.2 Ω ± 1%
5/5, < 500 mils
5/5, < 500 mils
DDR VTERM
(1.25V)
Rtt
DIMM to
DIMM
DIMM
to Rtt
DIMMs
Reference
90°
Figure 21
Figure 16
Note 2
7.5 mils
Figure 16
15 mils
Figure 21
< 0.8"
39

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