Reference Schematic For Single-Slot Parallel Mode - Intel Xeon Design Manual

8.2.5.9

Reference Schematic for Single-Slot Parallel Mode

Note that the following schematics are based on definition and simulation of the P64H2. These
schematics have not been fully validated.
Figure 8-12. Reference Schematic for Single-Slot Parallel Mode
PxPCLKO [0]
PxPCLKO [6]
PxPCLKI
PxAD[63:0]
PxC/BE[7:0]
PxPAR
PxPAR64
PxREQ64#
PxACK64#
PxFRAME#
PxIRDY#
Intel®
PxTRDY#
PxSTOP#
P64H2
PxDEVSEL#
PxPLOCK#
PxPERR#
PxSERR#
PxREQ[1:2]#
should be PxREQ[0]#
pulled to 3.3V
through 8.2K
PxGNT[0]#
PxGNT [5]# (HxRESETA#)
HPxSOD (HxPW RENA)
PxIRQ[14] (HxFAULTA#)
PxIRQ[12] (HxPRSNT1A)
PxIRQ[13] (HxPRSNT2A)
PxIRQ[11] (HxM66ENA)
HPxSLOT[2] (HXPCIXCAP1A)
HPxSLOT[1] (HXPCIXCAP2A)
HPxSOC (HxGNLEDA)
HPxSOL (HxAMLEDA)
PxIRQ[15] (HxSW ITCHA)
HPxSORR# (HxBUSENA#)
HPxSIL# (HxCLKENA#)
PxM66EN
PxPCIXCAP
HPxSOR# (HxRESETB#)
HPxSOLR (HxPW RENB)
PxIRQ[8] (HxPRSNT2B)
PxREQ[5]# (HxPRSNT1B)
PxREQ[4]# (HxM66ENB)
PxREQ[3]# (HXPCIXCAP1B)
HPxSLOT[0] (HXPCIXCAP2B)
PxIRQ[9] (HxFAULTB#)
HPxSIC (HxGNLEDNB)
HPxSID (HxAMLEDB)
PxGNT[4]# (HxBUSENB#)
PxGNT [3]# (HxCLKENB#)
PxIRQ[10] (HxSW ITCHB)
PW ROK
Input to PW ROK
Design Guide
33
33
64
330
330
3.3V
10K
8.2K
Switch
8.2K
3.3V
8.2K
8.2K
3.3V
8.2K
Inverter
100K
Pwren 1
Power
Fault#
Logic
ENB ENB
1K 1K
3.3V
3.3V
10K
8.2K
2.2K
Comparator
Comparator
®
Intel 82870P2 (P64H2)
CLK
PxAD[63:0]
PxC/BE[7:0]
PxPAR
PxPAR64
PxREQ64#
PxACK64#
PxF RAME#
PxIRDY#
PxT RDY#
PxSTOP#
PxDEVSEL#
PxPLOCK#
PxPERR#
PxSERR#
PxREQ0#
PxGNT0#
RST #
--12V --12V
+12V
+12V
+5V +5V
+3V +3V
PCI SLOT
3.3V
5K
M66EN
To run this slot in
33M Hz PCI m ode you
m ust hav e a pull-
dow n option or
equivalent logic on
M 66EN
3.3V
3.3V
5K
5K
SLOT 1 Present 1
SLOT 1 Present 2
3.3V 3.3V
5.6K 10K
10K
PCIXCAP
107