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Intel Xeon 7200 Series Manuals
Manuals and User Guides for Intel Xeon 7200 Series. We have
1
Intel Xeon 7200 Series manual available for free PDF download: Datasheet
Intel Xeon 7200 Series Datasheet (142 pages)
Data Sheet
Brand:
Intel
| Category:
Computer Hardware
| Size: 4.66 MB
Table of Contents
Table of Contents
3
Revision History
8
1 Introduction
9
Quad-Core Intel® Xeon® Processor 7300 Series Processor Features
10
Dual-Core Intel® Xeon® Processor 7200 Series Processor Features
10
Terminology
11
State of Data
13
References
13
2 Electrical Specifications
15
Front Side Bus and GTLREF
15
Decoupling Guidelines
15
VCC Decoupling
16
VTT Decoupling
16
Front Side Bus AGTL+ Decoupling
16
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
16
Front Side Bus Frequency Select Signals (BSEL[2:0])
17
PLL Power Supply
17
Voltage Identification (VID)
17
Core Frequency to FSB Multiplier Configuration
17
BSEL[2:0] Frequency Table
17
Voltage Identification Definition
19
Reserved, Unused, or Test Signals
20
Front Side Bus Signal Groups
20
FSB Signal Groups
21
CMOS Asynchronous and Open Drain Asynchronous Signals
22
Test Access Port (TAP) Connection
22
AGTL+ Signal Description Table
22
Non AGTL+ Signal Description Table
22
Signal Reference Voltages
22
Mixing Processors
23
Absolute Maximum and Minimum Ratings
23
Processor Absolute Maximum Ratings
23
Processor DC Specifications
24
Flexible Motherboard Guidelines (FMB)
25
Voltage and Current Specifications
25
Quad-Core Intel® Xeon® L7345 Processor Load Current Versus Time
27
Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current Versus Time
28
Quad-Core Intel® Xeon® X7350 Processor Load Current Versus Time
29
Tolerance Load Lines
31
Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance Load Lines
32
Load Lines
32
Quad-Core Intel® Xeon® L7345 Processor
33
CC Static and Transient Tolerance
33
Tolerance Load Lines
34
AGTL+ Signal Group DC Specifications
34
Platform Environmental Control Interface (PECI) DC Specifications
35
CMOS Signal Input/Output Group DC Specifications
35
Open Drain Signal Group DC Specifications
35
Smbus Signal Group DC Specifications
35
PECI DC Electrical Limits
36
Input Device Hysteresis
37
VCC Overshoot Specification
37
AGTL+ FSB Specifications
38
AGTL+ Bus Voltage Definitions
39
FSB Differential BCLK Specifications
39
Front Side Bus AC Specifications
40
Front Side Bus Common Clock AC Specifications
40
Front Side Bus Differential Clock AC Specifications
40
FSB Source Synchronous AC Specifications
41
Front Side Bus AC Specifications (Reset Conditions)
42
Miscellaneous GTL+ AC Specifications
42
TAP Signal Group AC Specifications
42
Smbus Signal Group AC Specifications
44
Processor AC Timing Waveforms
45
Electrical Test Circuit
46
TCK Clock Waveform
46
Differential Clock Crosspoint Specification
47
Differential Clock Waveform
47
BCLK Waveform at Processor Pad and Pin
48
FSB Common Clock Valid Delay Timing Waveform
48
FSB Source Synchronous 2X (Address) Timing Waveform
49
FSB Source Synchronous 4X (Data) Timing Waveform
50
TAP Valid Delay Timing Waveform
51
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
51
THERMTRIP# Power down Sequence
51
Smbus Timing Waveform
52
Smbus Valid Delay Timing Waveform
52
Voltage Sequence Timing Requirements
53
FERR#/PBE# Valid Delay Timing
54
VID Step Timings
54
VID Step Times and VCC Waveforms
55
VID Signal Group AC Specifications
44
3 Mechanical Specifications
57
Package Mechanical Drawing
57
Processor Package Assembly Sketch
57
Processor Package Drawing (Sheet 1 of 2)
58
Processor Package Drawing (Sheet 2 of 2)
59
Processor Component Keepout Zones
60
Top Side Board Keepout Zones (Part 1)
61
Top Side Board Keepout Zones (Part 2)
62
Bottom Side Board Keepout Zones
63
Board Mounting-Hole Keepout Zones
64
Volumetric Height Keep-Ins
65
Package Loading Specifications
66
Processor Loading Specifications
66
Package Handling Guidelines
67
Package Insertion Specifications
67
Processor Mass Specifications
67
Processor Materials
67
Processor Markings
68
Processor Topside Markings
68
Processor Bottom-Side Markings
68
Processor Pin-Out Coordinates
69
Processor Pin-Out Coordinates, Top View
69
4 Pin Listing
71
Pin Assignments
71
Pin Listing by Pin Name
71
Pin Listing by Pin Number
79
5 Signal Definitions
87
6 Thermal Specifications
95
Package Thermal Specifications
95
Quad-Core Intel® Xeon® E7300 Processor Thermal Specifications
96
Quad-Core Intel® Xeon® E7300 Processor Thermal Profile
97
Quad-Core Intel® Xeon® E7300 Processor Thermal Profile Table
97
Quad-Core Intel® Xeon® X7350 Processor Thermal Profile
98
Quad-Core Intel® Xeon® X7350 Processor Thermal Specifications
98
Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table
99
Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications
99
Quad-Core Intel® Xeon® L7345 Processor Thermal Profile
100
Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile
101
Dual-Core Intel® Xeon® Processor 7200 Series Thermal Specifications
101
Thermal Metrology
102
Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile
102
Processor Thermal Features
103
Thermal Monitor
103
Thermal Monitor Features
103
Thermal Monitor 2
104
On-Demand Mode
105
Thermal Monitor 2 Frequency and Voltage Ordering
105
FORCEPR# Signal
106
PROCHOT# Signal
106
THERMTRIP# Signal
106
Platform Environment Control Interface (PECI)
107
Introduction
107
PECI Topology
107
PECI Specifications
108
Conceptual Fan Control Diagram for a PECI-Based Platform
108
BREQ# Signal Assertion During Power on
109
PECI Address Assigned to Processor
109
Gettemp0() and Gettemp1() Error Codes
110
7 Features
111
Power-On Configuration Options
111
Clock Control and Low Power States
111
Power-On Configuration Option Pins
111
Normal State
112
HALT or Extended HALT State
112
Extended HALT Maximum Power
113
Stop-Grant State
114
Stop Clock State Machine
114
Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State
115
Enhanced Intel Speedstep® Technology
115
System Management Bus (Smbus) Interface
116
Smbus Device Addressing
117
Logical Schematic of Smbus Circuitry
117
PIROM and Scratch EEPROM Supported Smbus Transactions
118
Memory Device Smbus Addressing
118
Read Byte Smbus Packet
118
Write Byte Smbus Packet
118
Processor Information ROM (PIROM)
119
Processor Information ROM Data Sections
119
Checksums
137
Scratch EEPROM
137
128 Byte ROM Checksum Values
137
8 Boxed Processor Specifications
139
Introduction
139
Thermal Specifications
139
Boxed Processor Cooling Requirements
139
9 Debug Tools Specifications
141
Debug Port System Requirements
141
Logic Analyzer Interface (LAI)
141
Mechanical Considerations
141
Electrical Considerations
142
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