Clk33 Clock Group; Topology For Clk33 To Pci Device Down; Clk33 Routing Guidelines For Pci Device Down - Intel Xeon Design Manual

Platform Clock Routing Guidelines
4.1.4

CLK33 Clock Group

For the CLK33 clock group, the driver is the clock synthesizer 33 MHz clock output buffer, and the
receiver is the 33 MHz clock input buffer at the PCI devices on the PCI cards.
Figure 4-11. Topology for CLK33 to PCI Device Down
Clock
Driver
.
Table 4-6. CLK33 Routing Guidelines for PCI Device Down
Clock Group
Topology
Reference Plane
Characteristic Trace Impedance (Z
Trace Width
Trace Spacing
Trace Length – L1
Trace Length – L2
Resistor
Skew Requirements
46
L1
Parameter
CLK33
Point-to-Point
Ground referenced (contiguous over entire length)
50 Ω ± 10%
)
0
5 mils
25 mils
0.00" – 0.50"
3.00" – 9.0"
R1 = 33 Ω ± 5%
PCI device – PCI device skew max allowed by PCI Local Bus
Specification, Rev 2.2 is 2 ns. Therefore, length match with other
CLK33 signals within ± 1 ns.
L2
R1
Routing Guidelines
PCI Device,
FW H, BMC, SIO
Design Guide