Introduction; Reference Documentation; Reference Documents - Intel Xeon Design Manual

Intel
1.0

Introduction

This document is an addendum to the Intel
Compatible Platform Design Guide. It contains applied computing-specific guidelines, such as uni-
processor design guidelines, angled Double Data Rate (DDR) guidelines and single channel DDR
guidelines.
Carefully follow the design information and recommendations provided in this document. These
design guidelines have been developed to ensure maximum flexibility for system designers while
reducing the risk of board-related issues.
Note that the guidelines recommended in this document are based on experience and preliminary
simulation work done at Intel.
1.1

Reference Documentation

Table 1. Reference Documents (Sheet 1 of 2)
®
Intel E7501 Chipset Memory Controller Hub (MCH)
Datasheet
®
Intel Xeon™ Processor and Intel
Chipset Compatible Platform Design Guide
®
Intel Xeon™ Processor with 512 KB L2 Cache and
Intel E7500 Chipset Platform Design Guide
®
Intel Xeon™ Processor with 512 KB L2 Cache at
1.80 GHz to 2.40 GHz Datasheet
®
Intel E7500 Chipset Memory Controller Hub (MCH)
Datasheet
®
Intel 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
Datasheet
Intel 82801CA I/O Controller Hub 3 (ICH-3) Datasheet
®
Intel 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
Specification Update
®
Intel 82801CA I/O Controller Hub 3 (ICH3-S)
Specification Update
603-Pin Socket Design Guidelines
VRM 9.1 DC-DC Converter Design Guidelines
®
Intel Xeon™ Processor Voltage Regulator Down
(VRD) Design Guidelines
®
Intel Xeon™ Processor with 512 KB L2 Cache
System Compatibility Guidelines
®
Intel Xeon™ Processor Thermal Design Guidelines
®
Intel E7500 Chipset Thermal and Mechanical Design
Guidelines
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
Document
®
E7500/E7501
®
E7500/E7501 Chipset Compatible Platform
®
Xeon™ Processor and Intel
http://developer.intel.com/design/chipsets/datashts/
251927.htm
http://developer.intel.com/design/chipsets/designex/
251929.htm
http://developer.intel.com/design/chipsets/e7500/
guides/298649.htm
http://developer.intel.com/design/Xeon/datashts/
298642.htm
http://developer.intel.com/design/chipsets/e7500/
datashts/290730.htm
http://developer.intel.com/design/chipsets/e7500/
datashts/290732.htm
http://developer.intel.com/design/chipsets/e7500/
datashts/290733.htm
http://www.intel.com/design/chipsets/e7500/
specupdt/290735.htm
http://www.intel.com/design/chipsets/e7500/
specupdt/290739.htm
http://developer.intel.com/design/Xeon/guides/
249672.htm
http://developer.intel.com/design/Xeon/guides/
298646.htm
http://developer.intel.com/design/Xeon/guides/
298644.htm
http://developer.intel.com/design/Xeon/guides/
298645.htm
http://developer.intel.com/design/Xeon/guides/
298348.htm
http://developer.intel.com/design/chipsets/e7500/
guides/298647.htm
®
E7500/E7501 Chipset
Location
7