Front Side Bus Signal Groups - Intel Xeon Datasheet

Table 5.

Front Side Bus Signal Groups

Signal Group
AGTL+ Common Clock
Input
AGTL+ Common Clock I/O
AGTL+ Source
Synchronous I/O
AGTL+ Strobe I/O
AGTL Asynchronous Output Asynchronous
GTL+ Asynchronous Input
GTL+ Asynchronous Output
Front Side Bus Clock
TAP Input
TAP Output
Power/Other
NOTES:
1. Refer to
2. The Intel® Xeon™ processor with 800 MHz system bus only uses BR0# and BR1#. BR2# and BR3# must be
terminated to V
3. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See
4. These signals may be driven simultaneously by multiple agents (wired-OR).
Datasheet
Synchronous to BCLK[1:0]
Synchronous to BCLK[1:0]
Synchronous to assoc.
strobe
Synchronous to BCLK[1:0]
Asynchronous
Asynchronous
Clock
Synchronous to TCK
Synchronous to TCK
Power/Other
Section 4.0 for signal descriptions.
. For additional details regarding the BR[3:0]# signals, see
TT
Section 7.1 for details.
Intel® Xeon™ Processor with 800 MHz System Bus
Type
BPRI#, BR[3:1]#
RSP#, TRDY#
ADS#, AP[1:0]#, BINIT#
2,3
BR0# , DBSY#, DP[3:0]#, DRDY#, HIT#
4
HITM# , LOCK#, MCERR#
Signals
REQ[4:0]#,A[16:3]#
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
FERR#/PBE#, IERR#, PROCHOT#
A20M#, FORCEPR#, IGNNE#, INIT#
INTR, LINT1/NMI, SMI#
THERMTRIP#
BCLK1, BCLK0
tck, tdi, tms, trst#
TDO
BOOT_SELECT, BSEL[1:0], COMP[1:0],
GTLREF[3:0], ODTEN, OPTIMIZED/COMPAT#,
PWRGOOD, Reserved, SKTOCC#,
SLEW_CTRL, SMB_PRT, TEST_BUS,
TESTHI[6:0], THERMDA, THERMDC, V
V V
CCIOPLL,
V , VSSSENSE, V
SSA
1
Signals
2,3
, DEFER#, RESET#, RS[2:0]#,
4 4
, BNR# , BPM[5:0]#,
4
Associated Strobe
3
ADSTB0#
3
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
3
, LINT0/
3
, SLP#, STPCLK#
CC
, VCCSENSE, VID[5:0], V
CCPLL
, VIDPWRGD, VTTEN
TT
Section 4.0 and Section
4
,
, V ,
CCA
,
SS
7.1.
19