Single Channel Chip Select Routing; Single Channel Chip Select Topology - Intel Xeon Design Manual

®
Intel Xeon™ Processor and Intel
3.3.5

Single Channel Chip Select Routing

The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one
for each side). Chip selects for each DIMM must be length matched to the corresponding clock
within ± 875 mils and require parallel termination resistors (Rtt) to DDR VTERM.
Table 18. Single Channel Chip Select Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
MCH to DIMM1 Trace
Length
MCH to DIMM2 Trace
Length
Trace Length - DIMM to Rtt
Termination Resistor (Rtt)
MCH Breakout Guidelines
NOTES:
1. No length tuning required.
2. See the Intel
Figure 20. Single Channel Chip Select Topology
MCH
NOTES:
1. Unused CS n # signals are no connects.
2. Indicated lengths measure from the MCH component pin to the DIMM connector pin.
38
®
E7500/E7501 Chipset Compatible Platform
1-DIMM Solution
0°, 25°, 90°
1,2
50 Ω ± 10%
5 mils
15 mils
3.0" to 4.0"
Not Applicable
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
®
Xeon™ Processor and Intel
CS0#
CS1#
Channel A
CS2#
CS3#
MCH to DIMM
2-DIMM Solution
25°
CS[7:0]#
Point to Point
Ground
50 Ω ± 10%
5 mils
15 mils
3.0" to 4.0"
4.0" to 6.0"
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide .
DDR VTERM (1.25V)
Rtt
DIMMs
Platform Design Guide Addendum
2-DIMM Solution
Reference
90°
Figure 20
Figure 16
50 Ω ± 10%
Note 2
5 mils
Figure 16
15 mils
3.0" to 4.0"
4.0" to 6.0"
Figure 20
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
DIMM
to Rtt