Loop Clock Configuration; Loop Clock Configuration Routing Length Parameters - Intel Xeon Design Manual

8.1.4

Loop Clock Configuration

You must tie PxPCLKO[6] to PxPCLKI because this clock always runs and is needed by the
internal PCI PLLs to properly align output signals with the external clocks by removing clock
insertion delay. The PxPCLKO[6] signal does not have to be routed through a bus switch before
returning to PxPCLKI.
Figure 8-5. Loop Clock Configuration
Table 8-6. Loop Clock Configuration Routing Length Parameters
Clock Speed / Config
33 MHz / No HP
66 MHz / No HP
66 MHz / With HP
100 MHz / No HP
100 MHz / With HP
133 MHz / No HP
133 MHz / With HP
NOTES:
1. The clock signal and feedback loops are closely related. Refer to
Design Guide
PxPCLKO[6]
®
Intel
P64H2
PxPCLKI
L (inches)
fbo
3.5 – 5.5
4.5 – 5.5
0.25 – 1.0
≤ 1.0
4.5 – 5.5
0.25 – 1.0
3.5 – 4.0
®
Intel 82870P2 (P64H2)
L
fbo
Ω
33
L
fbi
L (inches)
fbi
2.9 – 7.9
3.9 – 4.9
7.0 – 12.0
1
L2 + 2.5
3.9 – 4.9
1
L2 + 2.5
5.5 – 5.7
Figure 8-4 for L2 and Figure 8-5 for L .
fbi
97