Halt Snoop State Or Snoop State; Sleep State - Intel Xeon Datasheet

Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven
(allowing the level to return to V
state. In addition, all other input pins on the front side bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should
only be deasserted one or more bus clocks after the deassertion of SLP#.
A transition to the Grant Snoop state will occur when the processor detects a snoop on the front
side bus (see
assertion of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch
interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
7.2.4

HALT Snoop State or Snoop State

The processor will respond to snoop or interrupt transactions on the front side bus while in Stop-
Grant state or in HALT Power Down state. During a snoop or interrupt transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the front
side bus has been serviced (whether by the processor or another agent on the front side bus) or the
interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will
return to the Stop-Grant state or HALT Power Down state, as appropriate.
7.2.5

Sleep State

The Sleep state is a very low power state in which each processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state
upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK
period. The SLP# pin should only be asserted when the processor is in the
Xeon™ processor with 800 MHz system bus, the SLP# pin may only be asserted when all logical
processors are in the Stop-Grant state. SLP# assertions while the processors are not in the Stop-
Grant state are out of specification and may results in illegal operation.
Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
Datasheet
) for minimum power drawn by the termination resistors in this
TT
Section 7.2.4). A transition to the Sleep state (see
Intel® Xeon™ Processor with 800 MHz System Bus
state.
°
Section 7.2.5) will occur with the
state. For Intel®
°
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