Table Of Contents - Intel Xeon Design Manual

Contents
1.0 Introduction...................................................................................................................................... 7
1.1 Reference Documentation .................................................................................................... 7
2.0 Uni-processor System Bus Routing Guidelines............................................................................... 9
2.1 Routing Guidelines for the 2X and 4X Signal Groups.........................................................11
2.1.1 Design Recommendations.....................................................................................12
2.2 Routing Guidelines for Common Clock Signals ..................................................................13
2.2.1 Wired-OR Signals ..................................................................................................13
2.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals...........................14
2.3.1 Asynchronous GTL+ Signals Driven by the Processor..........................................15
2.3.1.1
2.3.1.2
2.3.2 Asynchronous GTL+ Signals Driven by the Chipset..............................................17
2.3.2.1
2.3.3 BR[3:0] Routing Guidelines for Uni-processor Designs .........................................18
3.0 Memory Interface Routing Guidelines ...........................................................................................21
3.1 DIMM Types .......................................................................................................................22
3.2 Dual Channel DDR Overview .............................................................................................22
3.2.1 Dual Channel Source Synchronous Signal Group Routing ...................................23
3.2.2 Dual Channel Command Clock Routing ................................................................25
3.2.3 Dual Channel Source Clocked Signal Group Routing ...........................................26
3.2.4 Dual Channel Chip Select Routing ........................................................................27
3.2.5 Dual Channel Clock Enable Routing .....................................................................28
3.2.6 2.5 Volt Decoupling Requirements ........................................................................28
3.3 Single Channel DDR Overview...........................................................................................30
3.3.1 Unused Channel B.................................................................................................31
3.3.2 Single Channel Source Synchronous Signal Group Routing.................................32
3.3.3 Single Channel Command Clock Routing..............................................................36
3.3.4 Single Channel Source Clocked Signal Group Routing.........................................37
3.3.5 Single Channel Chip Select Routing......................................................................38
3.3.6 Single Channel Clock Enable Routing ...................................................................39
3.3.7 Single Channel DC Biasing Signals.......................................................................40
3.3.7.1
3.3.7.2
3.3.7.3
3.3.7.4
3.3.8 Single Channel DDR Signal Termination and Decoupling.....................................42
3.3.9 2.5 V Decoupling Requirements ............................................................................42
Platform Design Guide Addendum
Voltage Translation for FERR# ..............................................................15
Proper THERMTRIP# Usage.................................................................16
Voltage Translation for INIT# .................................................................17
Single Channel Receive Enable Signal (RCVEN#) ...............................40
Single Channel DDRCOMP ...................................................................41
Single Channel DDRVREF and ODTCOMP ..........................................41
Single Channel DDRCVO ......................................................................41
Contents
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