Design Recommendations - Intel Xeon Design Manual

®
Intel Xeon™ Processor and Intel
2.1.1

Design Recommendations

Below are the design recommendations for the data, address, strobes, and common clock signals.
For the following discussion, the pad is defined as the attach point of the silicon pad to the package
substrate.
DATA:
•
The pin to pin distance from the processor to the chipset should be between 3.5" to 10" (i.e.,
3.5" < L1 < 10"). Data signals of the same source synchronous group should be routed to the
same pad to pad length within ± 100 mils of the associated strobes. As a result, additional
traces will be added to some data nets on the system board in order for all trace lengths within
the same data group to be the same length (± 100 mils) from the pad of the processor to the pad
of the chipset. This length compensation will result in minimizing the source synchronous
skew that exists on the system bus. Without the length compensation the flight times between
a data signal and its strobe is different, which results in an inequity between the setup and hold
times.
Equation 1. Calculating Package Delta Addition to System Board Length for UP Systems
delta
net,strobe
† Strobe package length is the average of the strobe pair.
ADDRESS:
•
Address signals follow the same rules as data signals except they should be routed to the same
pad to pad length within ±200 mils of the associated strobes. Address signals may change
layers if the reference plane remains Vss and as long as the layers for a given group are all of
the same configuration (all stripline or all microstrip).
STROBE:
•
A strobe and its complement should be routed to a length equal to their corresponding data
group's median pad-to-pad length ±25 mils. This causes the strobe to be received closer to the
center of the data pulse, which results in reasonably comparable setup and hold times. A strobe
and its complement (xSTBp/n#) should be routed to ±25 mils of the same length. It is
recommended to simulate skew in order to determine the length that best centers the strobe for
a given system.
COMMON CLOCK:
•
Common clock signals should be routed to a minimum pin-to-pin system board length of 6"
and a maximum motherboard length of 10".
12
®
E7500/E7501 Chipset Compatible Platform
= (cpu_pkglen - cpu_pkglen
net
) + (chipset_pkglen
strobe† net
Platform Design Guide Addendum
- chipset_pkglen )
strobe