Ip53 Node Board - Silicon Graphics Origin 350 User Manual

3: Compute Module

IP53 Node Board

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The IP53 node board consists of the following components, most of which are discussed
in the subsections that follow.
• Two or four MIPS RISC processors (labeled CPU in Figure 3-3). Each processor has a
secondary L2 cache.
• Primary and secondary (L2) cache. (The primary cache is internal to the processor.
The L2 cache is labeled SRAM in Figure 3-3.)
• Eight dual inline memory module (DIMM) slots, for installation of DIMMs to
provide 1 to 8 GB of main memory to local memory bank pairs on your server. See
"Local Memory (DIMMs)" on page 116, for more information about DIMMs.
• Bedrock ASIC (or hub ASIC), which enables communication between the
processors, memory, and I/O devices.
• Serial ID EEPROM, which contains component information.
• Three VRMs, which convert incoming voltages to voltages required by components.
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