Processors (Cpus); Figure 3-3 Ip53 Node Board - Silicon Graphics Origin 350 User Manual

DIMM
1.1-V to 1.8-V Vcpu
VRMs
1.5-V V i/o
2.5-V Vmem

Processors (CPUs)

007-4566-001
Figure 3-3 IP53 Node Board
The R16000 processors, which are soldered to the IP53 node board, implement the 64-bit
MIPS IV instruction set architecture. The architecture gathers and decodes four
instructions per cycle and issues the instructions to five fully pipelined execution units.
It predicts conditional branches and executes instructions along the predicted path.
Each processor also uses a load/store architecture in which the processor does not
operate on data located in memory; instead, it loads the memory data into its registers
and then operates on the data. When the processor is finished manipulating the data, the
processor stores the data in memory.
SRAM
CPU
400
Bedrock
800
CPU
System Features
MegArray
connector
CPU
CPU
115