Bus Operation During Idle Mode - Intel 80C186EA User Manual

CLOCK GENERATION AND POWER MANAGEMENT
Halt Cycle
T4 or TI T1 TI TI TI
CLKOUT
Internal
Peripheral
Clock
CPU Core Clock
011
S2:0
ALE
A1119-0A
Figure 5-10. Entering Idle Mode
5.2.1.2

Bus Operation During Idle Mode

DMA requests, refresh requests and HOLD requests temporarily turn on the core clocks. If the
processor needs to run a DMA cycle during Idle mode, the internal core clock begins to toggle
on the falling CLKOUT edge three clocks after the processor samples the DMA request pin. After
one idle T-state, the processor runs the DMA cycle. The BIU uses the ready, wait state generation
and chip-select circuitry as necessary for DMA cycles during Idle mode. There is one idle T-state
after T4 before the internal core clock shuts off again.
5-13